Abstract: A processor includes a common instruction decode front end, e.g. fetch and decode stages, and a heterogeneous set of processing pipelines. A lower performance pipeline has fewer stages and may utilize lower speed/power circuitry. A higher performance pipeline has more stages and utilizes faster circuitry. The pipelines share other processor resources, such as an instruction cache, a register file stack, a data cache, a memory interface, and other architected registers within the system. In disclosed examples, the processor is controlled such that processes requiring higher performance run in the higher performance pipeline, whereas those requiring lower performance utilize the lower performance pipeline, in at least some instances while the higher performance pipeline is effectively inactive or even shut-off to minimize power consumption. The configuration of the processor at any given time, that is to say the pipeline(s) currently operating, may be controlled via several different techniques.