Patents by Inventor Thomas Cougar Van Eaton

Thomas Cougar Van Eaton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Data erasure in memory sub-systems
    Patent number: 11775198
    Abstract: Various examples are directed to memory systems comprising a component and a processing device. The memory system may comprise a plurality of blocks. A first portion of the plurality of blocks may be retired and a second portion of the plurality of blocks may be unretired. The processing device receives a sanitize operation for the plurality of blocks. The processing device initiates a first erase cycle at a first retired block of the plurality of blocks. The processing device determines that the first erase cycle was not successful and sets an erase indicator to false.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: October 3, 2023
    Assignee: Micron Technology, Inc.
    Inventors: Kevin R Brandt, Thomas Cougar Van Eaton
  • DATA ERASURE IN MEMORY SUB-SYSTEMS
    Publication number: 20220075549
    Abstract: Various examples are directed to memory systems comprising a component and a processing device. The memory system may comprise a plurality of blocks. A first portion of the plurality of blocks may be retired and a second portion of the plurality of blocks may be unretired. The processing device receives a sanitize operation for the plurality of blocks. The processing device initiates a first erase cycle at a first retired block of the plurality of blocks. The processing device determines that the first erase cycle was not successful and sets an erase indicator to false.
    Type: Application
    Filed: November 18, 2021
    Publication date: March 10, 2022
    Inventors: Kevin R. Brandt, Thomas Cougar Van Eaton
  • Data erasure in memory sub-systems
    Patent number: 11237755
    Abstract: Various examples are directed to memory systems comprising a component and a processing device. The memory system may comprise a plurality of blocks. A first portion of the plurality of blocks may be retired and a second portion of the plurality of blocks may be unretired. The processing device receives a sanitize operation for the plurality of blocks. The processing device initiates a first erase cycle at a first retired block of the plurality of blocks. The processing device determines that the first erase cycle was not successful and sets an erase indicator to false.
    Type: Grant
    Filed: March 19, 2020
    Date of Patent: February 1, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Kevin R Brandt, Thomas Cougar Van Eaton
  • DATA ERASURE IN MEMORY SUB-SYSTEMS
    Publication number: 20200218467
    Abstract: Various examples are directed to memory systems comprising a component and a processing device. The memory system may comprise a plurality of blocks. A first portion of the plurality of blocks may be retired and a second portion of the plurality of blocks may be unretired. The processing device receives a sanitize operation for the plurality of blocks. The processing device initiates a first erase cycle at a first retired block of the plurality of blocks. The processing device determines that the first erase cycle was not successful and sets an erase indicator to false.
    Type: Application
    Filed: March 19, 2020
    Publication date: July 9, 2020
    Inventors: Kevin R. Brandt, Thomas Cougar Van Eaton
  • Data erasure in memory sub-systems
    Patent number: 10628076
    Abstract: Various examples are directed to memory systems comprising a component and a processing device. The memory system may comprise a plurality of blocks. A first portion of the plurality of blocks may be retired and a second portion of the plurality of blocks may be unretired. The processing device receives a sanitize operation for the plurality of blocks. The processing device initiates a first erase cycle at a first retired block of the plurality of blocks. The processing device determines that the first erase cycle was not successful and sets an erase indicator to false.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: April 21, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kevin R Brandt, Thomas Cougar Van Eaton
  • DATA ERASURE IN MEMORY SUB-SYSTEMS
    Publication number: 20200104068
    Abstract: Various examples are directed to memory systems comprising a component and a processing device. The memory system may comprise a plurality of blocks. A first portion of the plurality of blocks may be retired and a second portion of the plurality of blocks may be unretired. The processing device receives a sanitize operation for the plurality of blocks. The processing device initiates a first erase cycle at a first retired block of the plurality of blocks. The processing device determines that the first erase cycle was not successful and sets an erase indicator to false.
    Type: Application
    Filed: October 1, 2018
    Publication date: April 2, 2020
    Inventors: Kevin R. Brandt, Thomas Cougar Van Eaton
  • Hard disk drive preamplifier write driver
    Patent number: 7133234
    Abstract: The present invention discloses an apparatus (160) comprising a common mode generator circuit (162) coupled to a current directing circuit adapted to provide current to a first write head connection node (170) and to a second write head connection node (172).
    Type: Grant
    Filed: July 8, 2003
    Date of Patent: November 7, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Bryan E. Bloodworth, Thomas Cougar Van Eaton