Abstract: A microprocessor including a random number generator within its instruction set architecture and made selectively available to program instructions of the instruction set architecture depending upon results of a self-test of the random number generator performed is disclosed. The microprocessor also includes a self-test unit that performs the self-test in response to a reset. The microprocessor also includes an instruction translator that translates instructions of the instruction set architecture, including instructions related exclusively to operation of the random number generator. The microprocessor generates a fault defined by the instruction set architecture in response to execution of one of the plurality of instructions related exclusively to operation of the random number generator if the self-test unit previously determined the random number generator is not operating properly.

Abstract: A technique is provided for performing modular multiplication. In one embodiment, an apparatus in a microprocessor is provided for accomplishing modular multiplication operations. The apparatus includes translation logic and execution logic. The translation logic receives a Montgomery multiplication instruction from a source therefrom, where the Montgomery multiplication instruction prescribes generation of a Montgomery product. The translation logic translates the Montgomery multiplication instruction into a sequence of micro instructions specifying sub-operations required to accomplish generation of the Montgomery product. The execution logic is operatively coupled to the translation logic. The execution logic receives the sequence of micro instructions, and performs the sub-operations to generate the Montgomery product.

Abstract: The present invention provides an apparatus and method for performing cryptographic operations on a plurality of message blocks within a processor to generate a message digest. In one embodiment, the apparatus includes translation logic and execution logic. The translation logic receives a cryptographic instruction from a source therefrom, where the cryptographic instruction prescribes generation of the message digest according to one of the cryptographic operations. The translation logic also translates the cryptographic instruction into a sequence of micro instructions specifying sub-operations required to accomplish generation of the message digest according to the one of the cryptographic operations. The execution logic is operatively coupled to the translation logic. The execution logic receives the sequence of micro instructions, and performs the sub-operations to generate the message digest.

Abstract: The present invention provides an apparatus and method for performing cryptographic operations on a plurality of input data blocks within a processor. In one embodiment, an apparatus for performing cryptographic operations is provided. The apparatus includes a cryptographic instruction, OFB mode logic, and execution logic. The cryptographic instruction is received by a computing device as part of an instruction flow executing on the computing device. The cryptographic instruction prescribes one of the cryptographic operations. The one of the cryptographic operations includes a plurality of OFB block cryptographic operations performed on a corresponding plurality of input text blocks. The OFB mode logic is operatively coupled to the cryptographic instruction. The OFB mode logic directs the computing device to update pointer registers and an initialization vector location for each of the plurality of CFB block cryptographic operations. The execution logic is operatively coupled to the OFB mode logic.

Abstract: The present invention provides an apparatus and method for performing hash operations. The apparatus provides an instruction for employment by a device. The instruction directs the device to perform a hash operation. The instruction has an opcode field and a repeat prefix field. The opcode field prescribes that the device accomplish the hash operation. The repeat prefix field is coupled to the opcode field and indicates that the hash operation prescribed by the instruction is to be accomplished on one or more message blocks.