Abstract: In a controller for a host machine such as an electrostatographic copier having a central processing unit module connected via a system bus to an input-output processing unit module, a direct memory access system functioning as part of the input-output processing unit module and operative to provide a high-speed means of refreshing and updating control registers in the host machine by direct accessing of memory in the central processing unit module. The direct memory access system may be programmed to synchronously refresh-update the host machine's control registers as in its normal mode and also asynchronously refresh-update the control registers as in the abnormal mode of a detected electrical disturbance in the electro-sensitive periphery surrounding the control registers, thus requiring restoring thereof.

Abstract: A non-volatile storage module as utilized in a controller for directing a plurality of control registers of a host machine. The controller includes a central processor that is communicatively coupled through a system bus having control data, and address lines to the module and host machine. The non-volatile storage module includes a data memory operative to interface with the system bus for storing data, and for input-output of the data therefrom through the system bus upon command of the central processor. In addition, the module further includes a power storage unit coupled to the data memory for distributing a plurality of power signals from the host machine through a plurality of critical and non-critical power lines to the data memory for providing a power source that may be utilized therein for a power down condition and for sensing a power down condition on the critical power line from the power storage unit for the switching thereof to the data memory.

Abstract: A controller for directing a host machine which is operative to include a central processor for program execution, a system bus controlled by the central processor for carrying data, address and control signals, and a data memory coupled to the system bus. Additionally included is a direct memory access moudle for conveyance through the system bus of a hold signal to the central processor upon receipt of an enabling signal, and upon acknowledgement for control assumptions of the system bus for generating address and state signals that will directly access the data memory for host machine update.