Abstract: A circuit for generating a bandgap voltage that is insensitive to temperature. The circuit includes an amplifier with a feedback loop having a high impedance output current mirror controlled by transistors connected to an output from the amplifier. The current mirror provides proportional currents to a pair of resistors that are connected to inputs to the amplifier, a first input receiving a temperature sensitive voltage from a first of the resistors, and a second input receiving a voltage that is a combination of a temperature sensitive voltage across a second of the resistors and a temperature sensitive offsetting voltage. The second resistor may be tapped to provide a selectable bandgap voltage. A reference voltage for operating the generator may be obtained from a voltage division of supply voltage by two resistors of the same type.

Abstract: A circuit for providing an input offset voltage to balance a fully differential amplifier may include two field effect transistors (FETs) in parallel conductive paths for receiving a current, an amplifier current source, a resistor connecting the FETs at their drains, and a second amplifier with inputs for an offset correction voltage and for a reference voltage on which the fully differential amplifier is to be balanced and outputs for providing control inputs to the FETs. The input offset voltage for balancing the fully differential amplifier is the difference between currents in the parallel paths times the resistance of the resistor. The circuit may be used to balance a fully differential amplifier in a telephone CODEC. The correction voltage may correct the total offset from the CODEC, or the offset introduced by a sign bit integrator that provides a correction for excursions of the same polarity in the CODEC.

Abstract: Methods of increasing the number of possible network configurations available during the manufacture of an integrated circuit hybrid balance network containing a fixed number of selectable network configurations in the manufactured network by including a network element selection layer programmable during the manufacturing process. The programming may be accomplished using ROM matrices programmed during or subsequent to the manufacturing process, or alternatively may be accomplished by the programming of the metal masks interconnecting the semiconductor portions of the IC without the necessity for changing the semiconductor masks.