Abstract: An embodiment includes an integrated circuit (IC) for using direct memory access (DMA) to initialize a programmable logic device (PLD), the IC operably coupled to the PLD. The IC includes an input/output (I/O) interface and a PLD interface. The I/O interface converts a signal format between the IC and the PLD. The PLD interface includes a configuration and status register, a data buffer, and pacing logic. The configuration and status register is adapted to manipulate a control line of the PLD to configure the PLD in a programming mode via the I/O interface. The data buffer temporarily holds PLD programming data received from a DMA control at a DMA speed. The pacing logic controls the speed of transmitting the PLD programming data to a programming port on the PLD via the I/O interface at a PLD programming speed.

Abstract: Processing within a device is controlled in order to avoid a deadlock situation. A local request engine of the device determines prior to making a request whether the port of the device that is to service the request is making forward progress in processing other requests. If forward progress is being made, then the request is forwarded to the port. Otherwise, the request is held. This avoids a deadlock situation and allows the device to remain operative even in partial recovery situations.

Abstract: Processing within a device is controlled in order to avoid a deadlock situation. A local request engine of the device determines prior to making a request whether the port of the device that is to service the request is making forward progress in processing other requests. If forward progress is being made, then the request is forwarded to the port. Otherwise, the request is held. This avoids a deadlock situation and allows the device to remain operative even in partial recovery situations.

Abstract: An embodiment includes using direct memory access (DMA) to initialize a programmable logic device (PLD). An aspect of the invention includes manipulating a control line of the PLD to configure the PLD in a programming mode. PLD programming data is received at a PLD interface from a DMA control at a DMA speed. The PLD interface controls access of a processor and the DMA control to a programming port on the PLD. The PLD interface includes a data buffer and pacing logic. The PLD programming data is written to the data buffer and read from the data buffer. The PLD programming data transmitted to the programming port on the PLD at a PLD programming speed. The pacing logic of the PLD interface controls the data transmission at the PLD programming speed, and the DMA control is configured to transform the PLD programming data while the processor performs other processing tasks.

Abstract: Methods, systems, and computer program products for using direct memory access (DMA) to initialize a programmable logic device (PLD) are provided. A method includes manipulating a control line of the PLD to configure the PLD in a programming mode, receiving PLD programming data from a DMA control at a DMA speed, and writing the PLD programming data to a data buffer. The method also includes reading the PLD programming data from the data buffer, and transmitting the PLD programming data to a programming port on the PLD at a PLD programming speed.

Abstract: Processing within a device is controlled in order to avoid a deadlock situation. A local request engine of the device determines prior to making a request whether the port of the device that is to service the request is making forward progress in processing other requests. If forward progress is being made, then the request is forwarded to the port. Otherwise, the request is held. This avoids a deadlock situation and allows the device to remain operative even in partial recovery situations.

Abstract: Processing within a device is controlled in order to avoid a deadlock situation. A local request engine of the device determines prior to making a request whether the port of the device that is to service the request is making forward progress in processing other requests. If forward progress is being made, then the request is forwarded to the port. Otherwise, the request is held. This avoids a deadlock situation and allows the device to remain operative even in partial recovery situations.

Abstract: An embodiment includes an integrated circuit (IC) for using direct memory access (DMA) to initialize a programmable logic device (PLD), the IC operably coupled to the PLD. The IC includes an input/output (I/O) interface and a PLD interface. The I/O interface converts a signal format between the IC and the PLD. The PLD interface includes a configuration and status register, a data buffer, and pacing logic. The configuration and status register is adapted to manipulate a control line of the PLD to configure the PLD in a programming mode via the I/O interface. The data buffer temporarily holds PLD programming data received from a DMA control at a DMA speed. The pacing logic controls the speed of transmitting the PLD programming data to a programming port on the PLD via the I/O interface at a PLD programming speed.

Abstract: An embodiment includes using direct memory access (DMA) to initialize a programmable logic device (PLD). An aspect of the invention includes manipulating a control line of the PLD to configure the PLD in a programming mode. PLD programming data is received at a PLD interface from a DMA control at a DMA speed. The PLD interface controls access of a processor and the DMA control to a programming port on the PLD. The PLD interface includes a data buffer and pacing logic. The PLD programming data is written to the data buffer and read from the data buffer. The PLD programming data transmitted to the programming port on the PLD at a PLD programming speed. The pacing logic of the PLD interface controls the data transmission at the PLD programming speed, and the DMA control is configured to transform the PLD programming data while the processor performs other processing tasks.

Abstract: A few inexpensive hardware facilities are incorporated in a tightly synchronized cross checked design. These facilities allow initialization software to quickly bring the two processors to the same state by rapid, repeated resets and execution of the initialization software. The resets are done in a way as to be transparent to the rest of the system and to the end user.

Abstract: A mechanism is provided for non-disruptive replacing of a first software module with a second software module in an embedded system. The mechanism includes copying update control code from the first software module to memory space outside a memory location of the first software module, and then replacing the first software module with a second software module by storing the second software module in memory at a location which at least partially overlies the first software module. The replacing includes executing the update control code copied from the first software module during the replacing. Upon completing storing of the second software module, execution of the second software module is begun without resetting the system.

Abstract: A few inexpensive hardware facilities are incorporated in a tightly synchronized cross checked design. These facilities allow initialization software to quickly bring the two processors to the same state by rapid, repeated resets and execution of the initialization software. The resets are done in a way as to be transparent to the rest of the system and to the end user.

Abstract: Methods, systems, and computer program products for using direct memory access (DMA) to initialize a programmable logic device (PLD) are provided. A method includes manipulating a control line of the PLD to configure the PLD in a programming mode, receiving PLD programming data from a DMA control at a DMA speed, and writing the PLD programming data to a data buffer. The method also includes reading the PLD programming data from the data buffer, and transmitting the PLD programming data to a programming port on the PLD at a PLD programming speed.

Abstract: A few inexpensive hardware facilities are incorporated in a tightly synchronized cross checked design. These facilities allow initialization software to quickly bring the two processors to the same state by rapid, repeated resets and execution of the initialization software. The resets are done in a way as to be transparent to the rest of the system and to the end user.

Abstract: A method of writing to cache including initiating a write operation to a cache. In a first operational mode, the presence or absence of a write miss is detected and if a write miss is absent, writing data to the cache and if a write miss is present, retrieving the data from a further memory and writing the data to the cache based on least recently used logic. In a second operational mode, the cache is placed in a memory mode and the data is written to the cache based on an address regardless of whether a write miss is present or absent.