Patents by Inventor Thomas David Dryburgh

Thomas David Dryburgh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Providing memory management functionality using aggregated memory management units (MMUs)
    Patent number: 10019380
    Abstract: Providing memory management functionality using aggregated memory management units (MMUs), and related apparatuses and methods are disclosed. In one aspect, an aggregated MMU is provided, comprising a plurality of input data paths including each including plurality of input transaction buffers, and a plurality of output paths each including a plurality of output transaction buffers. Some aspects of the aggregated MMU additionally provide one or more translation caches and/or one or more hardware page table walkers The aggregated MMU further includes an MMU management circuit configured to retrieve a memory address translation request (MATR) from an input transaction buffer, perform a memory address translation operation based on the MATR to generate a translated memory address field (TMAF), and provide the TMAF to an output transaction buffer. The aggregated MMU also provides a plurality of output data paths, each configured to output transactions with resulting memory address translations.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: July 10, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Serag Monier GadelRab, Jason Edward Podaima, Ruolong Liu, Alexander Miretsky, Paul Christopher John Wiercienski, Kyle John Ernewein, Carlos Javier Moreira, Simon Peter William Booth, Meghal Varia, Thomas David Dryburgh
  • PROVIDING MEMORY MANAGEMENT FUNCTIONALITY USING AGGREGATED MEMORY MANAGEMENT UNITS (MMUs)
    Publication number: 20170091116
    Abstract: Providing memory management functionality using aggregated memory management units (MMUs), and related apparatuses and methods are disclosed. In one aspect, an aggregated MMU is provided, comprising a plurality of input data paths including each including plurality of input transaction buffers, and a plurality of output paths each including a plurality of output transaction buffers. Some aspects of the aggregated MMU additionally provide one or more translation caches and/or one or more hardware page table walkers The aggregated MMU further includes an MMU management circuit configured to retrieve a memory address translation request (MATR) from an input transaction buffer, perform a memory address translation operation based on the MATR to generate a translated memory address field (TMAF), and provide the TMAF to an output transaction buffer. The aggregated MMU also provides a plurality of output data paths, each configured to output transactions with resulting memory address translations.
    Type: Application
    Filed: September 25, 2015
    Publication date: March 30, 2017
    Inventors: Serag Monier GadelRab, Jason Edward Podaima, Ruolong Liu, Alexander Miretsky, Paul Christopher John Wiercienski, Kyle John Ernewein, Carlos Javier Moreira, Simon Peter William Booth, Meghal Varia, Thomas David Dryburgh