Abstract: A network device can include a main processor and a packet processor. A method is provided that includes storing a table of values in the packet processor, using the packet processor to receive from the main processor a value that can be used to update the table of values, and using acceleration hardware in the packet processor to update the table of values based on the value received from the main processor without any additional interaction with the software running on the main processor.

Abstract: A method and system for emulating physical layer (L1) connectivity between distant computing devices. Existing solutions require that the computing devices or end points directly connect to a same interconnecting (or network) device and/or employ network devices requiring awareness of the communication protocol used between the end points. Further, existing solutions typically fail to match the ingress and egress clock rates. These restrictions limit scaling of the solutions, confine the end points to a physical co-location, and/or fail to transport or replicate the physical properties (e.g., errors, proprietary signaling, clock frequency, etc.) of the data stream transmitted between the end points. The disclosed method and system overcome these limitations through implementation of a L1 connectivity abstraction between computing devices across a network, and through clock rate reconstruction using a data buffer state controlled phase lock loop (PLL) mechanism.

Abstract: A method and system for emulating physical layer (L1) connectivity between distant computing devices. Existing solutions require that the computing devices or end points directly connect to a same interconnecting (or network) device and/or employ network devices requiring awareness of the communication protocol used between the end points. Further, existing solutions typically fail to match the ingress and egress clock rates. These restrictions limit scaling of the solutions, confine the end points to a physical co-location, and/or fail to transport or replicate the physical properties (e.g., errors, proprietary signaling, clock frequency, etc.) of the data stream transmitted between the end points. The disclosed method and system overcome these limitations through implementation of a L1connectivity abstraction between computing devices across a network, and through clock rate reconstruction using a data buffer state controlled phase lock loop (PLL) mechanism.

Abstract: A method and network device for forwarding data packets. Specifically, the method and network device disclosed herein separate the known data packet forwarding architecture in network devices, often implemented using a single component, into two components. In implementing the pair of components, functionalities directed to forwarding data packets versus buffering data packets, based on the detection of data packet collisions, are segregated. Further, the segregation of these functionalities reduces the latency observed in the communication of the data packets from these network devices to other devices to which these network devices may be connected through a network.

Abstract: Embodiments of the invention relate to systems and methods for distributing information. In one or more embodiments of the invention, the method includes receiving, at a replicator, a single data stream originating from a data source, wherein the single data stream comprises a first plurality of data units from the data source; replicating, by the replicator, the single data stream to obtain a first replicated data stream and a second replicated data stream; transmitting the first replicated data stream to a first data recipient; and transmitting the second replicated data stream to a second data recipient.

Abstract: Embodiments of the invention relate to systems and methods for distributing information. In one or more embodiments of the invention, the method includes receiving, at a replicator, a single data stream originating from a data source, wherein the single data stream comprises a first plurality of data units from the data source; replicating, by the replicator, the single data stream to obtain a first replicated data stream and a second replicated data stream; transmitting the first replicated data stream to a first data recipient; and transmitting the second replicated data stream to a second data recipient.

Abstract: Methods and systems for performing clock domain crossing. The method may include receiving a start signal from an ingress domain delay device at a first egress domain delay device. The start signal may be received at a first rising edge of an egress domain clock cycle. The method may also include receiving, from the first egress domain delay device at a start receive device, the start signal at a second rising edge of the egress domain clock cycle. The second rising edge may be N egress domain clock cycles after the first rising edge. The method may also include incrementing, in response to receipt of the start signal by the start receive device, a buffer read pointer of the buffer by at least N buffer addresses, and reading, after incrementing the buffer read pointer, a second data unit from the buffer at a location indicated by the buffer read pointer.

Abstract: A bitstream representing an Ethernet frame is received over a physical medium. Encoded Ethernet blocks are recovered from the bitstream. The Ethernet blocks are descrambled and provided to downstream switching logic, intact, without removing the synchronization bits that were added during the encoding process. More particularly, the intact descrambled Ethernet block is divided into smaller-sized data words; the size of the data words being an integer multiple of the size of the Ethernet block.

Abstract: In general, the invention relates to a gearbox. The gearbox may include a controller comprising circuity and is configured to make a first determination that an available data amount at a first clock cycle is greater than a required data amount and that no idle Ethernet Block is being processed, wherein the available data amount at the first clock cycle comprises an unaligned data word, based on the first determination, generate a first aligned data word comprising at least a portion of the unaligned data word, and transmit the first aligned data word to a transmit port.

Abstract: Embodiments of the present disclosure include techniques for generating accurate time stamps. In one embodiment, a first timing reference signal corresponding to a first clock domain is combined with a first clock signal corresponding to a second clock domain to produce a second timing reference signal that includes quantization noise. The second timing reference signal is filtered to remove the quantization noise and generate a filtered timing reference signal. The filtered timing reference signal may be sampled in the second clock domain to obtain a time stamp. In one embodiment, a phase locked loop (PLL) is used as the filter. The PLL may generate first and second ramps that correspond to time. One of the ramps may be sampled to obtain a time stamp, for example.

Abstract: A bitstream representing an Ethernet frame is received over a physical medium. Encoded Ethernet blocks are recovered from the bitstream. The Ethernet blocks are descrambled and provided to downstream switching logic, intact, without removing the synchronization bits that were added during the encoding process. More particularly, the intact descrambled Ethernet block is divided into smaller-sized data words; the size of the data words being an integer multiple of the size of the Ethernet block.

Abstract: In general, the invention relates to a gearbox. The gearbox may include a controller comprising circuity and is configured to make a first determination that an available data amount at a first clock cycle is greater than a required data amount and that no idle Ethernet Block is being processed, wherein the available data amount at the first clock cycle comprises an unaligned data word, based on the first determination, generate a first aligned data word comprising at least a portion of the unaligned data word, and transmit the first aligned data word to a transmit port.

Abstract: Embodiments of the present disclosure include techniques for generating accurate time stamps. In one embodiment, a first timing reference signal corresponding to a first clock domain is combined with a first clock signal corresponding to a second clock domain to produce a second timing reference signal that includes quantization noise. The second timing reference signal is filtered to remove the quantization noise and generate a filtered timing reference signal. The filtered timing reference signal may be sampled in the second clock domain to obtain a time stamp. In one embodiment, a phase locked loop (PLL) is used as the filter. The PLL may generate first and second ramps that correspond to time. One of the ramps may be sampled to obtain a time stamp, for example.

Abstract: A method and network device for forwarding data packets. Specifically, the method and network device disclosed herein separate the known data packet forwarding architecture in network devices, often implemented using a single component, into two components. In implementing the pair of components, functionalities directed to forwarding data packets versus buffering data packets, based on the detection of data packet collisions, are segregated. Further, the segregation of these functionalities reduces the latency observed in the communication of the data packets from these network devices to other devices to which these network devices may be connected through a network.

Abstract: Embodiments of the invention relate to systems and methods for distributing information. In one or more embodiments of the invention, the method includes receiving, at a replicator, a single data stream originating from a data source, wherein the single data stream comprises a first plurality of data units from the data source; replicating, by the replicator, the single data stream to obtain a first replicated data stream and a second replicated data stream; transmitting the first replicated data stream to a first data recipient; and transmitting the second replicated data stream to a second data recipient.

Abstract: Methods and systems for performing clock domain crossing. The method may include receiving a start signal from an ingress domain delay device at a first egress domain delay device. The start signal may be received at a first rising edge of an egress domain clock cycle. The method may also include receiving, from the first egress domain delay device at a start receive device, the start signal at a second rising edge of the egress domain clock cycle. The second rising edge may be N egress domain clock cycles after the first rising edge. The method may also include incrementing, in response to receipt of the start signal by the start receive device, a buffer read pointer of the buffer by at least N buffer addresses, and reading, after incrementing the buffer read pointer, a second data unit from the buffer at a location indicated by the buffer read pointer.

Abstract: Methods and apparatus are disclosed using a random indication to map items to paths and to recirculate or delay the sending of a particular item when a destination over its mapped path is unreachable, including, but not limited to the context of sending of packets across multiple paths in a packet switching system. In one implementation, a set of items is buffered, with the set of items including a first and second sets of items. The items in the first set of items are forwarded over a set of paths in a first configuration. The set of paths is reconfigured into a second configuration, and the items in the second set of items are forwarded over the set of paths in the second configuration. In one implementation, a recirculation buffer is used to hold items not immediately sent. In one implementation, the paths are reconfigured in a random fashion.

Abstract: A method of determining a geographical location of an asset tracking device, includes searching, by the asset tracking device, for available location determination schemes at the geographical location, selecting one of the available location determination schemes, and determining coordinates of the geographical location using the selected location determination scheme. Some embodiments also include making a decision based, at least in part, upon the geographical location coordinates determined by using the selected location determination scheme. Some embodiments include transmitting a location message, the location message including the coordinates of the geographical location and an indication as to the selected location determination scheme.

Abstract: A GPS receiver includes baseband resources for simultaneous determination of carrier frequency shift and code chip offset. Reduction in the power consumption of a receiver is achieved by managing the sampling rate of an analog-to-digital converter, the intermediate frequency of the RF front end, and the front end bandwidth so these are appropriate to the current function of the receiver. In a GPS receiver during signal tracking, the IF, front end bandwidth, and ADC sampling rate are set as high as possible; during signal acquisition, the IF and front end bandwidth are set to relatively low values, and the ADC sample rate is set to a high value; and during ephemeris download, the IF, front end bandwidth, and the ADC sample rate are set to relatively low values. When a low battery condition is detected, the IF, front end bandwidth, and the ADC sample rate are set to relatively low values regardless of whether the GPS receiver is in the signal acquisition mode, signal tracking mode, or ephemeris download mode.

Abstract: Methods and apparatus are disclosed for an adaptive rate control mechanism reactive to flow control messages in a packet switching system and other communications and computer systems. Typically, a multiplicative increase and exponential decrease technique is used to throttle traffic. Backpressure feedback is used to calculate the initial rate at which to allow traffic after backpressure is deasserted. This reduces the probability of underrun of buffers (e.g., too little traffic being carried). The adjustment to the initial rate is made by measuring the time between the XON and XOFF in factor periods. Then a target XON time is subtracted. If the result is positive (i.e., the measured XON time was too long), the rate is multiplicatively increased (e.g., by a factor of two to the difference). If the result is negative (i.e., the measured XON time was too short), the rate is exponentially decreased (e.g., by the square root).