Abstract: Embodiments of the invention relate to systems and methods for distributing information. In one or more embodiments of the invention, the method includes receiving, at a replicator, a single data stream originating from a data source, wherein the single data stream comprises a first plurality of data units from the data source; replicating, by the replicator, the single data stream to obtain a first replicated data stream and a second replicated data stream; transmitting the first replicated data stream to a first data recipient; and transmitting the second replicated data stream to a second data recipient.

Abstract: A network device can include a main processor and a packet processor. A method is provided that includes storing a table of values in the packet processor, using the packet processor to receive from the main processor a value that can be used to update the table of values, and using acceleration hardware in the packet processor to update the table of values based on the value received from the main processor without any additional interaction with the software running on the main processor.

Abstract: Techniques for parsing FPGA counter data records in a network device with an FPGA are provided. In one set of embodiments these techniques include ingesting, by the network device, a metadata file associated with an application image programmed in (or configured to be programmed in) the FPGA, where the metadata file includes definitions of counter data record types that are used (i.e., reported via counter messages) by the application image. The techniques further include receiving a counter message from the FPGA that includes one or more counter data records and, for each record, retrieving the ingested definition of that record's type and parsing the record in accordance with the definition.

Abstract: A method of operating a network device is provided. The method can include obtaining incoming data packets, conveying the incoming data packets through a parallel data bus, and using a demultiplexer to split the incoming data packets being conveyed through the parallel data bus onto a plurality of separate independent data paths within the network device. The method can further include using a multiplexer to aggregate or merge data packets from the plurality of data paths onto an egress parallel data bus.

Abstract: A network device can include a main processor and a packet processor. A method is provided that includes storing a table of values in the packet processor, using the packet processor to receive from the main processor a value that can be used to update the table of values, and using acceleration hardware in the packet processor to update the table of values based on the value received from the main processor without any additional interaction with the software running on the main processor.

Abstract: A network device can include a main processor and a packet processor. A method is provided that includes storing a table of values in the packet processor, using the packet processor to receive from the main processor a value that can be used to update the table of values, and using acceleration hardware in the packet processor to update the table of values based on the value received from the main processor without any additional interaction with the software running on the main processor.

Abstract: Embodiments of the invention relate to systems and methods for distributing information. In one or more embodiments of the invention, the method includes receiving, at a replicator, a single data stream originating from a data source, wherein the single data stream comprises a first plurality of data units from the data source; replicating, by the replicator, the single data stream to obtain a first replicated data stream and a second replicated data stream; transmitting the first replicated data stream to a first data recipient; and transmitting the second replicated data stream to a second data recipient.

Abstract: A network device can include a main processor and a packet processor. The packet processor can include multiple physical interfaces operable to communicate with external processors using different communications protocols, data storage elements, and a multi-interface bridge that enables the external processors to access the data storage elements using a common address map. The packet processor can include multiple input-output ports, host interface counter circuitry coupled to an external processor via one or more register interfaces, and client interface counter circuitry configured to accumulate count values for at least some of the input-output ports and to write the accumulated count values into memory on the host interface counter circuitry. The accumulated count values can be published by the host interface counter circuitry to a local or remote server via a statistics publishing interface.

Abstract: A network device can include a main processor and a packet processor. A method is provided that includes storing a table of values in the packet processor, using the packet processor to receive from the main processor a value that can be used to update the table of values, and using acceleration hardware in the packet processor to update the table of values based on the value received from the main processor without any additional interaction with the software running on the main processor.

Abstract: A method for distributing information includes: receiving, at a replicator, a single data stream originating from a data source where the single data stream includes a first plurality of data units from the data source; replicating, by the replicator, the single data stream to obtain a first replicated data stream and a second replicated data stream; adding a delay between the first plurality of data units in the single data stream before replicating the single data stream; transmitting the first replicated data stream to a first data recipient using a first communication channel; and transmitting the second replicated data stream to a second data recipient using a second communication channel. The replication of the single data stream is performed by a lower layer device to obtain the first replicated data stream and the second replicated data stream substantially synchronously.

Abstract: A network device can include a main processor and a packet processor. A method is provided that includes storing a table of values in the packet processor, using the packet processor to receive from the main processor a value that can be used to update the table of values, and using acceleration hardware in the packet processor to update the table of values based on the value received from the main processor without any additional interaction with the software running on the main processor.

Abstract: A method and system for emulating physical layer (L1) connectivity between distant computing devices. Existing solutions require that the computing devices or end points directly connect to a same interconnecting (or network) device and/or employ network devices requiring awareness of the communication protocol used between the end points. Further, existing solutions typically fail to match the ingress and egress clock rates. These restrictions limit scaling of the solutions, confine the end points to a physical co-location, and/or fail to transport or replicate the physical properties (e.g., errors, proprietary signaling, clock frequency, etc.) of the data stream transmitted between the end points. The disclosed method and system overcome these limitations through implementation of a L1 connectivity abstraction between computing devices across a network, and through clock rate reconstruction using a data buffer state controlled phase lock loop (PLL) mechanism.

Abstract: A method and system for emulating physical layer (L1) connectivity between distant computing devices. Existing solutions require that the computing devices or end points directly connect to a same interconnecting (or network) device and/or employ network devices requiring awareness of the communication protocol used between the end points. Further, existing solutions typically fail to match the ingress and egress clock rates. These restrictions limit scaling of the solutions, confine the end points to a physical co-location, and/or fail to transport or replicate the physical properties (e.g., errors, proprietary signaling, clock frequency, etc.) of the data stream transmitted between the end points. The disclosed method and system overcome these limitations through implementation of a L1connectivity abstraction between computing devices across a network, and through clock rate reconstruction using a data buffer state controlled phase lock loop (PLL) mechanism.

Abstract: A method and network device for forwarding data packets. Specifically, the method and network device disclosed herein separate the known data packet forwarding architecture in network devices, often implemented using a single component, into two components. In implementing the pair of components, functionalities directed to forwarding data packets versus buffering data packets, based on the detection of data packet collisions, are segregated. Further, the segregation of these functionalities reduces the latency observed in the communication of the data packets from these network devices to other devices to which these network devices may be connected through a network.

Abstract: Embodiments of the invention relate to systems and methods for distributing information. In one or more embodiments of the invention, the method includes receiving, at a replicator, a single data stream originating from a data source, wherein the single data stream comprises a first plurality of data units from the data source; replicating, by the replicator, the single data stream to obtain a first replicated data stream and a second replicated data stream; transmitting the first replicated data stream to a first data recipient; and transmitting the second replicated data stream to a second data recipient.

Abstract: Embodiments of the invention relate to systems and methods for distributing information. In one or more embodiments of the invention, the method includes receiving, at a replicator, a single data stream originating from a data source, wherein the single data stream comprises a first plurality of data units from the data source; replicating, by the replicator, the single data stream to obtain a first replicated data stream and a second replicated data stream; transmitting the first replicated data stream to a first data recipient; and transmitting the second replicated data stream to a second data recipient.

Abstract: Methods and systems for performing clock domain crossing. The method may include receiving a start signal from an ingress domain delay device at a first egress domain delay device. The start signal may be received at a first rising edge of an egress domain clock cycle. The method may also include receiving, from the first egress domain delay device at a start receive device, the start signal at a second rising edge of the egress domain clock cycle. The second rising edge may be N egress domain clock cycles after the first rising edge. The method may also include incrementing, in response to receipt of the start signal by the start receive device, a buffer read pointer of the buffer by at least N buffer addresses, and reading, after incrementing the buffer read pointer, a second data unit from the buffer at a location indicated by the buffer read pointer.

Abstract: A bitstream representing an Ethernet frame is received over a physical medium. Encoded Ethernet blocks are recovered from the bitstream. The Ethernet blocks are descrambled and provided to downstream switching logic, intact, without removing the synchronization bits that were added during the encoding process. More particularly, the intact descrambled Ethernet block is divided into smaller-sized data words; the size of the data words being an integer multiple of the size of the Ethernet block.

Abstract: In general, the invention relates to a gearbox. The gearbox may include a controller comprising circuity and is configured to make a first determination that an available data amount at a first clock cycle is greater than a required data amount and that no idle Ethernet Block is being processed, wherein the available data amount at the first clock cycle comprises an unaligned data word, based on the first determination, generate a first aligned data word comprising at least a portion of the unaligned data word, and transmit the first aligned data word to a transmit port.

Abstract: Embodiments of the present disclosure include techniques for generating accurate time stamps. In one embodiment, a first timing reference signal corresponding to a first clock domain is combined with a first clock signal corresponding to a second clock domain to produce a second timing reference signal that includes quantization noise. The second timing reference signal is filtered to remove the quantization noise and generate a filtered timing reference signal. The filtered timing reference signal may be sampled in the second clock domain to obtain a time stamp. In one embodiment, a phase locked loop (PLL) is used as the filter. The PLL may generate first and second ramps that correspond to time. One of the ramps may be sampled to obtain a time stamp, for example.