Patents by Inventor Thomas Detzel

Thomas Detzel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220123138
    Abstract: A method includes providing a semiconductor body including a plurality of two-dimensional charge carrier gas channels, forming a gate fin by forming a pair of gate trenches in an upper surface of the semiconductor body, the pair of gate trenches exposing each one of two-dimensional charge carrier gas channels, providing source and drain contacts that are electrically connected to each one of the plurality of two-dimensional charge carrier gas channels, providing a gate structure that is configured to control a conductive connection between the source and drain contacts, wherein providing the gate structure includes forming a layer of doped type III-nitride semiconductor material that covers the gate fin and extends into the gate trenches, and forming a conductive gate electrode on top of the layer of doped type III-nitride semiconductor material.
    Type: Application
    Filed: December 28, 2021
    Publication date: April 21, 2022
    Inventors: Thomas Detzel, Gerhard Prechtl, Oliver Haeberlen
  • Patent number: 11257941
    Abstract: A transistor device includes a gate fin that is a segment of a semiconductor body disposed between a pair of gate trenches formed in an upper surface of the semiconductor body, a plurality of two-dimensional charge carrier gas channels disposed at different vertical depths within the gate fin, source and drain contacts arranged on either side of the gate fin in a current flow direction of the gate fin, the source and drain contacts each being electrically connected to each one of the two-dimensional charge carrier gas channels, and a gate structure that is configured to control a conductive connection between the source and drain contacts. The gate structure includes a region of doped type III-nitride semiconductor material that covers the gate fin and extends into the gate trenches, and a conductive gate electrode formed over the region of doped type III-nitride semiconductor material.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: February 22, 2022
    Assignee: Infineon Technologies Austria AG
    Inventors: Thomas Detzel, Gerhard Prechtl, Oliver Haeberlen
  • Publication number: 20210234028
    Abstract: A transistor device includes a gate fin that is a segment of a semiconductor body disposed between a pair of gate trenches formed in an upper surface of the semiconductor body, a plurality of two-dimensional charge carrier gas channels disposed at different vertical depths within the gate fin, source and drain contacts arranged on either side of the gate fin in a current flow direction of the gate fin, the source and drain contacts each being electrically connected to each one of the two-dimensional charge carrier gas channels, and a gate structure that is configured to control a conductive connection between the source and drain contacts. The gate structure includes a region of doped type III-nitride semiconductor material that covers the gate fin and extends into the gate trenches, and a conductive gate electrode formed over the region of doped type III-nitride semiconductor material.
    Type: Application
    Filed: January 28, 2020
    Publication date: July 29, 2021
    Inventors: Thomas Detzel, Gerhard Prechtl, Oliver Haeberlen
  • Patent number: 10446469
    Abstract: A semiconductor device includes a base element and a copper element over the base element. The copper element includes a layer stack having at least two copper layers and at least one intermediate conductive layer of a material different from copper. The at least two copper layers and the at least one intermediate conductive layer are alternately stacked over each other.
    Type: Grant
    Filed: July 22, 2016
    Date of Patent: October 15, 2019
    Assignee: Infineon Technologies AG
    Inventors: Thomas Detzel, Johann Gross, Robert Illing, Maximilian Krug, Sven Gustav Lanzerstorfer, Michael Nelhiebel, Werner Robl, Michael Rogalli, Stefan Woehlert
  • Publication number: 20160329263
    Abstract: A semiconductor device includes a base element and a copper element over the base element. The copper element includes a layer stack having at least two copper layers and at least one intermediate conductive layer of a material different from copper. The at least two copper layers and the at least one intermediate conductive layer are alternately stacked over each other.
    Type: Application
    Filed: July 22, 2016
    Publication date: November 10, 2016
    Inventors: Thomas Detzel, Johann Gross, Robert Illing, Maximilian Krug, Sven Gustav Lanzerstorfer, Michael Nelhiebel, Werner Robl, Michael Rogalli, Stefan Woehlert
  • Patent number: 9418937
    Abstract: An integrated circuit includes a base element and a copper element over the base element, the copper element having a thickness of at least 5 ?m and a ratio of average grain size to thickness of less than 0.7.
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: August 16, 2016
    Assignee: Infineon Technologies AG
    Inventors: Thomas Detzel, Johann Gross, Robert Illing, Maximilian Krug, Sven Gustav Lanzerstorfer, Michael Nelhiebel, Werner Robl, Michael Rogalli, Stefan Woehlert
  • Patent number: 9059182
    Abstract: An arrangement is employed in a semiconductor device having a semiconductor body, the semiconductor body having a surface. The arrangement includes a surface portion on which a first metallization layer is arranged, and an alignment pattern arranged between the surface portion and the first metallization layer.
    Type: Grant
    Filed: September 14, 2006
    Date of Patent: June 16, 2015
    Assignee: Infineon Technologies AG
    Inventors: Hubert Maier, Thomas Detzel
  • Patent number: 8603912
    Abstract: A power semiconductor component and a method for the production of a power semiconductor component are disclosed. According to one embodiment of the invention, a topmost metallization region that is provided is formed in a manner extended laterally and outside contacts formed, in such a way that, as a result, a protection and sealing material region to be provided is formed, while avoiding electrically insulating additional protection and sealing layers that are usually to be provided.
    Type: Grant
    Filed: September 6, 2011
    Date of Patent: December 10, 2013
    Assignee: Infineon Technologies AG
    Inventors: Josef Maynollo, Thomas Detzel
  • Patent number: 8502274
    Abstract: Power transistor cells are formed in a cell array of an integrated circuit. Contact vias may electrically connect a metal structure above the cell array and the power transistor cells. A connecting line electrically connects a first element arranged in the cell array and a second element arranged in a peripheral region. A portion of the connecting line is arranged between the metal structure and the cell array and runs between a first axis and a second axis which are arranged parallel and at a distance to each other. The distance is greater than a width of the connecting line portion. The connecting line portion is tangent to both the first axis and the second axis. Shear-induced material transport along the connecting line is reduced by shortening critical portions or by exploiting grain boundary effects. The reliability of an insulator structure covering the connecting line is increased.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: August 6, 2013
    Assignee: Infineon Technologies AG
    Inventors: Kurt Matoy, Thomas Detzel, Michael Nelhiebel, Arno Zechmann, Stefan Decker, Robert Illing, Sven Gustav Lanzerstorfer, Christian Djelassi, Bernhard Auer, Stefan Woehlert
  • Publication number: 20130147047
    Abstract: An integrated circuit includes a base element and a copper element over the base element, the copper element having a thickness of at least 5 ?m and a ratio of average grain size to thickness of less than 0.7.
    Type: Application
    Filed: December 9, 2011
    Publication date: June 13, 2013
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Thomas Detzel, Johann Gross, Robert Illing, Maximilian Krug, Sven Gustav Lanzerstorfer, Michael Nelhiebel, Werner Robl, Michael Rogalli, Stefan Woehlert
  • Publication number: 20110318883
    Abstract: A power semiconductor component and a method for the production of a power semiconductor component are disclosed. According to one embodiment of the invention, a topmost metallization region that is provided is formed in a manner extended laterally and outside contacts formed, in such a way that, as a result, a protection and sealing material region to be provided is formed, whilst avoiding electrically insulating additional protection and sealing layers that are usually to be provided.
    Type: Application
    Filed: September 6, 2011
    Publication date: December 29, 2011
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Josef Maynollo, Thomas Detzel
  • Patent number: 8039931
    Abstract: A power semiconductor component and a method for the production of a power semiconductor component are disclosed. According to one embodiment of the invention, a topmost metallization region that is provided is formed in a manner extended laterally and outside contacts formed, in such a way that, as a result, a protection and sealing material region to be provided is formed, whilst avoiding electrically insulating additional protection and sealing layers that are usually to be provided.
    Type: Grant
    Filed: November 28, 2005
    Date of Patent: October 18, 2011
    Assignee: Infineon Technologies AG
    Inventors: Josef Maynollo, Thomas Detzel
  • Patent number: 7834427
    Abstract: An integrated circuit including a semiconductor arrangement, a power semiconductor component and an associated production method is disclosed. One embodiment includes a carrier substrate, a first interconnect layer, formed on the carrier substrate and has at least one cutout, an insulating filling layer, formed on the first interconnect layer and the carrier substrate and fills at least one cutout, an SiON layer, formed on the filling layer, and a second interconnect layer, formed over the SiON layer.
    Type: Grant
    Filed: February 28, 2007
    Date of Patent: November 16, 2010
    Assignee: Infineon Technologies Austria AG
    Inventors: Thomas Detzel, Hubert Maier, Kai-Alexander Schreiber, Stefan Woehlert, Uwe Hoeckele
  • Patent number: 7531439
    Abstract: Methods for forming an integrated semiconductor circuit arrangement are disclosed. In one embodiment, a semiconductor circuit with a first semiconductor circuit region and with a second semiconductor circuit region is formed in each case in a semiconductor material region. A first metallization layer is applied to the structure thus obtained. A protective material region is then formed. A second metallization layer is subsequently applied, which is then also patterned. Afterward, the first metallization layer together with the protective material region is then patterned.
    Type: Grant
    Filed: May 26, 2005
    Date of Patent: May 12, 2009
    Assignee: Infineon Technologies AG
    Inventors: Johann Rieger, Stefan Lipp, Hans Peter Zeindl, Thomas Detzel, Hubert Maier
  • Publication number: 20080179669
    Abstract: An integrated circuit including a semiconductor arrangement, a power semiconductor component and an associated production method is disclosed. One embodiment includes a carrier substrate, a first interconnect layer, formed on the carrier substrate and has at least one cutout, an insulating filling layer, formed on the first interconnect layer and the carrier substrate and fills at least one cutout, an SiON layer, formed on the filling layer, and a second interconnect layer, formed over the SiON layer.
    Type: Application
    Filed: February 28, 2007
    Publication date: July 31, 2008
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Thomas Detzel, Hubert Maier, Kai-Alexander Schreiber, Stefan Woehlert, Uwe Hoeckele
  • Publication number: 20070063318
    Abstract: An arrangement is employed in a semiconductor device having a semiconductor body, the semiconductor body having a surface. The arrangement includes a surface portion on which a first metallization layer is arranged, and an alignment pattern arranged between the surface portion and the first metallization layer.
    Type: Application
    Filed: September 14, 2006
    Publication date: March 22, 2007
    Applicant: Infineon Technologies AG
    Inventors: Hubert Maier, Thomas Detzel
  • Patent number: 7132726
    Abstract: An integrated semiconductor circuit having a first and a second portion of a substrate, in which a power semiconductor circuit structure and a logic circuit structure are respectively formed. The metallization having a power metal layer and an in relative terms thinner logic metal layer, the two metal layers being located directly above one another in this order, without an intermetal dielectric between them, only in the first portion above the power semiconductor circuit structure, and an uninterrupted conductive barrier layer being located at least between the power metal layer and the intermediate oxide layer and also between the power metal layer and the contact regions and electrode portions of the power semiconductor circuit structure which it contact-connects, and to a method for fabricating it.
    Type: Grant
    Filed: January 18, 2005
    Date of Patent: November 7, 2006
    Assignee: Infineon Technologies AG
    Inventors: Michael Rueb, Thomas Detzel
  • Publication number: 20060145342
    Abstract: A power semiconductor component and a method for the production of a power semiconductor component are disclosed. According to one embodiment of the invention, a topmost metallization region that is provided is formed in a manner extended laterally and outside contacts formed, in such a way that, as a result, a protection and sealing material region to be provided is formed, whilst avoiding electrically insulating additional protection and sealing layers that are usually to be provided.
    Type: Application
    Filed: November 28, 2005
    Publication date: July 6, 2006
    Inventors: Josef Maynollo, Thomas Detzel
  • Publication number: 20060014371
    Abstract: Methods for forming an integrated semiconductor circuit arrangement are disclosed. In one embodiment, a semiconductor circuit with a first semiconductor circuit region and with a second semiconductor circuit region is formed in each case in a semiconductor material region. A first metallization layer is applied to the structure thus obtained. A protective material region is then formed. A second metallization layer is subsequently applied, which is then also patterned. Afterward, the first metallization layer together with the protective material region is then patterned.
    Type: Application
    Filed: May 26, 2005
    Publication date: January 19, 2006
    Inventors: Johann Rieger, Stefan Lipp, Hans Zeindl, Thomas Detzel, Hubert Maier
  • Publication number: 20050179068
    Abstract: An integrated semiconductor circuit having a first and a second portion of a substrate, in which a power semiconductor circuit structure and a logic circuit structure are respectively formed. The metallization having a power metal layer and an in relative terms thinner logic metal layer, the two metal layers being located directly above one another in this order, without an intermetal dielectric between them, only in the first portion above the power semiconductor circuit structure, and an uninterrupted conductive barrier layer being located at least between the power metal layer and the intermediate oxide layer and also between the power metal layer and the contact regions and electrode portions of the power semiconductor circuit structure which it contact-connects, and to a method for fabricating it.
    Type: Application
    Filed: January 18, 2005
    Publication date: August 18, 2005
    Inventors: Michael Rueb, Thomas Detzel