Abstract: The specification describes an MCM package which contains both a digital MCM and an RF MCM in a stacked configuration. The package contains means for isolating RF signals from digital signals. In one case the digital MCM substrate is attached to the system substrate and the RF MCM substrate is attached to the digital MCM substrate. Solder bumps are used for attachment in an arrangement resembling a BGA. For high density packages, at least the digital MCM comprises stacked IC chips. In the embodiment with the RF MCM substrate on the top of the stack, Passive Through Interconnections (PTIs) are made through the digital MCM substrate, and electrically isolated therefrom. The passive through interconnections are made through the solder bumps between boards and interconnected using a passive (with respect to the digital MCM board) through hole. Both the RF ground and the RF input can be isolated using PTIs. For additional isolation, the solder bumps comprising the PTIs are shielded with a Faraday cage.

Abstract: The specification describes electrical testing strategies for multi-chip modules (MCMs). The MCMs are fabricated on double sided substrates, which are then solder bump bonded to a motherboard to form a BGA package. Untested chips are attached permanently to one side of the substrate to form a partially completed MCM package (PCMP), and the PCMPs are tested. PCMPs that pass are then completed by assembling known good die on the other side of the substrate.

Abstract: The specification describes a multi-chip IC package in which IC chips are flip-chip bonded to both sides of a flexible substrate. The upper (or lower) surface of the flexible substrate is bonded to a rigid support substrate with openings in the support substrate to accommodate the IC chips bonded to the upper (or lower) surface of the flexible substrate. In a preferred embodiment a plurality of IC memory chips are mounted on one side of the flexible substrate and one or more logic chips to the other. A very thin flexible substrate is used to optimize the length of through hole interconnections between the memory and logic devices. If logic chips are flip-chip mounted in the cavity formed by the openings, a heat sink plate can be used to both cap the cavity and make effective thermal contact the backside of the logic chips.

Abstract: The specification describes a high density IC BGA package in which one or more IC chips are wire bonded to a BGA substrate in a conventional fashion and the BGA substrate is solder ball bonded to a printed wiring board. The standoff between the BGA substrate and the printed wiring board to which it is attached provides a BGA gap which, according to the invention, accommodates one or more IC chips flip-chip bonded to the underside of the BGA substrate. The recognition that state of the art IC chips, especially chips that are thinned, can easily fit into the BGA gap makes practical this efficient use of the BGA gap. The approach of the invention also marries wire bond technology with high packing density flip-chip assembly to produce a low cost, high reliability, state of the art IC package.

Abstract: The specification describes packaging assemblies for micro-electronic machined mechanical systems (MEMS). The MEMS devices in these package assemblies are based on silicon MEMS devices on a silicon support and the MEMS devices and the silicon support are mechanically isolated from foreign materials. Foreign materials pose the potential for differential thermal expansion that deleteriously affects optical alignment in the MEMS devices. In a preferred embodiment the MEMS devices are enclosed in an all-silicon chamber. Mechanical isolation is also aided by using a pin contact array for interconnecting the silicon support substrate for the MEMS devices to the next interconnect level. The use of the pin contact array also allows the MEMS devices to be easily demountable for replacement or repair.

Abstract: The specification describes an MCM package which contains both a digital MCM and an RF MCM in a stacked configuration. The package contains means for isolating RF signals from digital signals. In one case the digital MCM substrate is attached to the system substrate and the RF MCM substrate is attached to the digital MCM substrate. Solder bumps are used for attachment in an arrangement resembling a BGA. For high density packages, at least the digital MCM comprises stacked IC chips. In the embodiment with the RF MCM substrate on the top of the stack, Passive Through Interconnections (PTIs) are made through the digital MCM substrate, and electrically isolated therefrom. The passive through interconnections are made through the solder bumps between boards and interconnected using a passive (with respect to the digital MCM board) through hole. Both the RF ground and the RF input can be isolated using PTIs. For additional isolation, the solder bumps comprising the PTIs are shielded with a Faraday cage.

Abstract: The specification describes electrical testing strategies for multi-chip modules (MCMs). The MCMs are fabricated on double sided substrates, which are then solder bump bonded to a motherboard to form a BGA package. Untested chips are attached permanently to one side of the substrate to form a partially completed MCM package (PCMP), and the PCMPs are tested. PCMPs that pass are then completed by assembling known good die on the other side of the substrate.

Abstract: The specification describes interconnection strategies for micro-electronic machined mechanical systems (MEMS). Typical MEMS device array comprise a large number of individual mechanical devices each electrically driven by multi-chip modules (MCMs). High density interconnection is achieved by mounting the MCMs mounted on both sides of a system interconnection substrate. Overall interconnection length is reduced by locating the MCMs in a common circuit driving a given mechanical element on opposite sides of the system interconnection substrate and interconnecting them using vias through the substrate. Rapid replacement/repair is facilitated by mounted all active elements in sockets using contact pin arrays for electrical connections. In service reliability is obtained by providing spare sockets for redundant MCMs.

Abstract: The specification describes methods for the manufacture of printed circuit cards which allow for final testing, including burn-in if required, of multiples of printed circuit cards as an integrated process panel prior to final packaging and singulation. This desired sequence of operations is made possible by the addition of arrays of test contacts at the edge of the integrated process panel where the test contacts can be accessed with an insertion test apparatus.

Abstract: The specification describes interconnection assemblies for silicon-on-silicon multichip modules. The silicon-on-silicon MCMs are mounted on epoxy/glass laminates which have a coefficient of thermal expansion (CTE) that essentially matches the CTE of silicon. In the preferred embodiment the assembly is a PC card with card edge connectors, i.e. without fixed solder interlevel interconnections, so that the CTE of the epoxy laminate comprising the card can be modified without regard to potential mismatch with a mother board.

Abstract: The specification describes a recessed chip MCM package with integrated electromagnetic shielding. The surfaces of the cavity which houses the IC devices are coated with metallization. The normally exposed top and side surfaces of the MCM package are also metallized. A solder wall is provided on the interconnect PCB which seals the gap between the MCM tile and the PCB interconnect substrate. The solder wall can be formed using standard solder bump technology, and the seal between the MCM and the PCB may be made during the same reflow operation that is used to flip-chip bond the MCM tile to the PCB.

Abstract: The specification describes a high density I/O IC package in which the IC chip is bonded to a silicon intermediate interconnection substrate (IIS), and the IIS is wire bonded to a printed wiring board. This marriage of wire bond technology with high density I/O IC chips results in a low cost, high reliability, state of the art IC package.

Abstract: The specification describes methods for manufacturing thin tiles for IC packages using thinning techniques. The method includes the step of thinning the IC devices in chip form. This is achieved at the final stage of assembly where the chips are flip-chip bonded to the substrate and the backside of the chips is exposed for thinning. Using this approach, final chip thickness of the order of 2-8 mils can be produced and overall package thickness is dramatically reduced.

Abstract: The specification describes a method for dispensing IC chips from a chip carrier tape for a flip-chip assembly operation. In a conventional assembly operation, the solder bumped side of the chip is the top side of the chip as loaded on the tape, and is normally the side of the chip that engages the head of the pick tool. For flip-chip assembly it is necessary to invert the chip for solder bonding to an interconnect substrate. In the technique of the invention, the chip carrier tape is inverted and inserted into the dispensing machine upside down. The IC chips are then ejected through the back of the tape instead of being lifted from the from of the tape. In this way the pick tool head engages the back side of the solder bumped chip and the chip is in the proper orientation for flip-chip placement and bonding on the interconnect substrate. Carrier tapes designed for through-tape dispensing are also disclosed.

Abstract: The specification describes a recessed chip IC package in which the IC chip is bonded to a silicon translator, and power and ground planes for IC power and ground interconnections are formed on separate interconnect levels of the translator. The multilevel interconnection capability of the translator allows crossovers, and allows power and ground pins from the IC chip to be both isolated from signal I/Os, and consolidated into fewer interconnections going to the next board level. The thermal mismatch between the silicon translator and conventional printed wiring board materials is addressed by using an interposer which is essentially a ball grid array of plated-through holes that transfers the interconnect pattern from the translator to the printed wiring board. The interposer may have a composition with a coefficient of thermal expansion (CTE) that lies between the CTE of silicon and the CTE of the board material. It may also be provided with holes or slots for additional stress relief.

Abstract: The specification describes a recessed chip IC package in which the IC chip is bonded to a translator, and power and ground planes for IC power and ground interconnections are formed on separate interconnect levels of the translator. The multilevel interconnection capability of the translator allows crossovers, and allows power and ground pins from the IC chip to be both isolated from signal I/Os, and consolidated into fewer interconnections going to the next board level. The translator also has a large area outboard of the IC chip area to allow fan out from high pin count chips to large pitch interconnection sites for interconnection to the next board level.

Abstract: A multichip module is assembled using flip-chip bonding technology, a stencil printable solder paste and standard surface mount equipment for interconnecting signaling input/output contact pads on devices within such multichip module.

Abstract: A fragile device, such as an integrated circuit chip or a multichip assembly, is packaged by first dispensing a sol surrounding the sides of the device. The sol is laterally confined by means of a rim member typically made of a pre-molded plastic material. The amount of the sol dispensed is not sufficient to run over the top of the rim member. The sol is then heated to form a gel. If desired, a cover member can be put into place onto the top surface of the rim member, for the purpose of additional mechanical protection of the fragile device, for example.

Abstract: The specification describes an interconnect strategy for memory chip packages to reduce or eliminate alpha particle contamination from the use of high lead solder interconnections in the vicinity of semiconductor memory cells. In the primary embodiment a high tin solder is recommended. A multi-layer under bump metallization is described that is compatible with high tin solders and flip-chip solder bump technology.

Abstract: The specification describes a method for dispensing IC chips from a chip carrier tape for a flip-chip assembly operation. In a conventional assembly operation, the solder bumped side of the chip is the top side of the chip as loaded on the tape, and is normally the side of the chip that engages the head of the pick tool. For flip-chip assembly it is necessary to invert the chip for solder bonding to an interconnect substrate. In the technique of the invention, the chip carrier tape is inverted and inserted into the dispensing machine upside down. The IC chips are then ejected through the back of the tape instead of being lifted from the from of the tape. In this way the pick tool head engages the back side of the solder bumped chip and the chip is in the proper orientation for flip-chip placement and bonding on the interconnect substrate.