Abstract: An interposer, and integrated circuit including an interposer, has a lower surface adapted for bump mounting and an upper surface adapted for copper bonding. An interposer layer includes active interposers and passive interposers. Bridges connect interposers in the interposer layer to produce a functionally large interposer from smaller interposer dies. A core may overlap more than one interposer in the interposer layer. Active interposers are disposed around the edge of the core with passive interposers beneath the core to facilitate heat dissipation.

Abstract: A device may include a host substrate with two or more circuit regions, one or more first stacks electrically connected to the circuit regions, and one or more second stacks providing electrical connections between the circuit regions. At least some of the second stacks may include an insulator wafer bonded to a die, where the die is bonded to at least one of the circuit regions. At least one of the second stacks may include a power distribution pathway to provide the electrical power to at least one of the circuit regions, which may include includes electrically-conductive vias through the insulator wafer and the die or capacitors in the die. Further, the die of at least one of the one or more second stacks may include electrical pathways to provide electrical connections between at least two of the two or more circuit regions.

Abstract: A semiconductor structure includes a III-V semiconductor structure; a first electrode; a first barrier layer disposed over the first electrode; a first adhesion layer disposed over the first electrode; a first passivation layer disposed over the first adhesion layer; a dielectric layer disposed over the first passivation layer; a second passivation layer disposed over the dielectric layer; a second adhesion layer disposed over the second passivation layer; a second barrier layer disposed over the second adhesion layer; and a second electrode disposed over the second barrier layer.

Abstract: A thermally conductive and electrically insulating layer is provided over a semiconductor structure.

Abstract: A heterojunction bipolar transistor (HBT) amplifier device includes transistor fingers arranged in parallel on a substrate. Each transistor finger includes a base/collector mesa stripe shaving a trapezoidal shaped cross-section with sloping sides, and having a base stacked on a collector; a set of emitter mesa stripes arranged on the base/collector mesa stripe; and emitter metallization formed over the set of emitter mesa stripes and the base/collector mesa. The emitter metallization includes a center portion for providing electrical and thermal connectivity to the emitter mesa stripes and extended portions extending beyond the base and overlapping onto the sloping sides of the base/collector mesa stripe for increasing thermal coupling to the collector. A common conductive pillar is formed over the transistor fingers for providing electrical and thermal conductivity.

Abstract: An apparatus, a semiconductor package including the apparatus and a method are disclosed. The apparatus includes a semiconductor die having second stages of power amplifier disposed over a module substrate. The module substrate includes a plurality of layers, pluralities of vias, and pluralities of routing layers for heat dissipation and electrical connections.

Abstract: A heterojunction bipolar transistor (HBT) amplifier device includes transistor fingers arranged in parallel on a substrate. Each transistor finger includes a base/collector mesa stripe shaving a trapezoidal shaped cross-section with sloping sides, and having a base stacked on a collector; a set of emitter mesa stripes arranged on the base/collector mesa stripe; and emitter metallization formed over the set of emitter mesa stripes and the base/collector mesa. The emitter metallization includes a center portion for providing electrical and thermal connectivity to the emitter mesa stripes and extended portions extending beyond the base and overlapping onto the sloping sides of the base/collector mesa stripe for increasing thermal coupling to the collector. A common conductive pillar is formed over the transistor fingers for providing electrical and thermal conductivity.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes an electrically conductive layer disposed over a substrate. A moisture barrier layer is disposed over the substrate and between the substrate and the electrically conductive layer. A dielectric layer is disposed over the moisture barrier layer. The dielectric layer has an elastic modulus that is lower than an elastic modulus of the moisture barrier layer.

Abstract: An apparatus, a semiconductor package including the apparatus and a method are disclosed. The apparatus includes a semiconductor die having second stages of power amplifier disposed over a module substrate. The module substrate includes a plurality of layers, pluralities of vias, and pluralities of routing layers for heat dissipation and electrical connections.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes an electrically conductive layer disposed over a substrate. A moisture barrier layer is disposed over the substrate and between the substrate and the electrically conductive layer. A dielectric layer is disposed over the moisture barrier layer. The dielectric layer has an elastic modulus that is lower than an elastic modulus of the moisture barrier layer.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes an electrically conductive layer disposed over a substrate. A moisture barrier layer is disposed over the substrate and between the substrate and the electrically conductive layer. A dielectric layer is disposed over the moisture barrier layer. The dielectric layer has an elastic modulus that is lower than an elastic modulus of the moisture barrier layer.

Abstract: A thermally conductive and electrically insulating layer is provided over a semiconductor structure.

Abstract: A semiconductor structure is disclosed. The semiconductor structure includes an electrically conductive layer disposed over a substrate. A moisture barrier layer is disposed over the substrate and between the substrate and the electrically conductive layer. A dielectric layer is disposed over the moisture barrier layer. The dielectric layer has an elastic modulus that is lower than an elastic modulus of the moisture barrier layer.

Abstract: A method of fabricating Group III-V semiconductor metal oxide semiconductor (MOS) and III-V MOS devices are described.

Abstract: A tiered integrated circuit (IC) assembly includes stacks of a limited number of ICs coupled to each other and arranged in a first direction across a base tier and a second tier. The base tier includes ICs and a data bridge. Each of the ICs includes a respective array of through silicon vias (TSVs) arranged in parallel with the first direction. The data bridge includes submicron metal interconnects (densely spaced electrical conductors) arranged in a plane that is substantially orthogonal to the first direction. The second tier is adjacent to the base tier and includes respective high-performance ICs different from the ICs of the base tier. The TSVs provide power and ground paths to the ICs in the second tier. In an example embodiment, the ICs in the second tier support one or more data bridges for connecting adjacent stacks.

Abstract: An integrated device includes a lower layer pattern on a semiconductor substrate. The lower layer pattern includes a first region including first electrical devices and a second region including second electrical devices and electrically nonconductive dummy devices. A first device density of the first electrical devices in the first region is substantially greater than a second device density of the second electrical devices in the second region. A partially-planarizing dielectric layer is disposed on the lower layer pattern so as to cover the first electrical devices, the second electrical devices, and the electrically nonconductive dummy devices. The average height of the partially-planarizing dielectric layer in the first region is approximately the same as the average height in the second region. Through-holes are formed in the first region, and an electrically conductive material is disposed in the through-holes.

Abstract: A method for protecting input/output (I/O) circuits on an integrated circuit (IC) from electrostatic discharge (ESD) is disclosed. The method includes the steps of providing at least one protective device on a surface of a first semiconductor die and applying a conductive shorting layer over a select region of the surface to electrically couple at least one metallic stud to the at least one protective device. After bonding the IC die to a second IC die and/or testing one or more core circuits, the conductive shorting layer is removed to enable high-speed I/O connections arranged in the select region of the semiconductor die. An IC assembly includes first and second semiconductor dice. One of the dice includes a protective device along a surface. An electrically conductive shorting layer couples the protective device to a conductive element that is further coupled to I/O circuit elements.

Abstract: A tiered integrated circuit (IC) assembly includes stacks of a limited number of ICs coupled to each other and arranged in a first direction across a base tier and a second tier. The base tier includes ICs and a data bridge. Each of the ICs includes a respective array of through silicon vias (TSVs) arranged in parallel with the first direction. The data bridge includes submicron metal interconnects (densely spaced electrical conductors) arranged in a plane that is substantially orthogonal to the first direction. The second tier is adjacent to the base tier and includes respective high-performance ICs different from the ICs of the base tier. The TSVs provide power and ground paths to the ICs in the second tier. In an example embodiment, the ICs in the second tier support one or more data bridges for connecting adjacent stacks.

Abstract: A pixel including a substrate of a first conductivity type and having a surface, a photodetector of a second conductivity type that is opposite the first conductivity type, a floating diffusion region of the second conductivity type, a transfer region between the photodetector and the floating diffusion, a gate positioned above the transfer region and partially overlapping the photodetector, and a pinning layer of the first conductivity type extending at least across the photodetector from the gate.

Abstract: A vertical tri-color sensor having vertically stacked blue, green, and red pixels detects at least blue and green components of incident light by converting the blue and green components to surface plasmons.