Patents by Inventor Thomas Dyer Bonifield

Thomas Dyer Bonifield has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12033936
    Abstract: An electronic device has a substrate and first and second metallization levels with a resonant circuit. The first metallization level has a first dielectric layer on a side of the substrate, and a first metal layer on the first dielectric layer. The second metallization level has a second dielectric layer on the first dielectric layer and the first metal layer, and a second metal layer on the second dielectric layer. The electronic device includes a first plate in the first metal layer, and a second plate spaced apart from the first plate in the second metal layer to form a capacitor. The electronic device includes a winding in one of the first or second metal layers and coupled to one of the first or second plates in a resonant circuit.
    Type: Grant
    Filed: October 10, 2022
    Date of Patent: July 9, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Klaas De Haan, Mikhail Valeryevich Ivanov, Tobias Bernhard Fritz, Swaminathan Sankaran, Thomas Dyer Bonifield
  • Publication number: 20240120270
    Abstract: An integrated circuit includes a semiconductor substrate and a plurality of dielectric layers over the semiconductor substrate, including a top dielectric layer. A metal plate or metal coil is located over the top dielectric layer; a metal ring is located over the top dielectric layer and substantially surrounds the metal plate or metal coil. A protective overcoat overlies the metal ring and overlies the metal plate or metal coil. A trench opening is formed through the protective overcoat, with the trench opening exposing the top dielectric layer between the metal plate/coil and the metal ring, the trench opening substantially surrounding the metal plate or metal coil.
    Type: Application
    Filed: December 4, 2023
    Publication date: April 11, 2024
    Inventors: Jeffrey Alan West, Thomas Dyer Bonifield
  • Publication number: 20240120367
    Abstract: An electronic device includes a first dielectric layer above a semiconductor layer, lower-bandgap dielectric layer above the first dielectric layer, the lower-bandgap dielectric layer having a bandgap energy less than a bandgap energy of the first dielectric layer, a first capacitor plate above the lower-bandgap dielectric layer in a first plane of first and second directions, a second dielectric layer above the first capacitor plate, a second capacitor plate above the second dielectric layer in a second plane of the first and second directions, the first and second capacitor plates spaced apart from one another along a third direction, and a conductive third capacitor plate above the second dielectric layer in the second plane, the third capacitor plate spaced apart from the second capacitor plate in the second plane.
    Type: Application
    Filed: December 20, 2023
    Publication date: April 11, 2024
    Inventors: Elizabeth Costner Stewart, Thomas Dyer Bonifield, Jeffrey Alan West, Byron Lovell Williams
  • Publication number: 20240113042
    Abstract: A microelectronic device including an isolation device. The isolation device includes a lower isolation element, an upper isolation element, and an inorganic dielectric plateau between the lower isolation element and the upper isolation element. The inorganic dielectric plateau contains an upper etch stop layer and a lower etch stop layer between the upper isolation element and the lower isolation element. The upper etch stop layer provides an end point signal during the plateau etch process which provides feedback on the amount of inorganic dielectric plateau which has been etched. The lower etch stop layer provides a traditional etch stop function to provide for a complete plateau etch and protection of an underlying metal bond pad. The inorganic dielectric plateau also contains alternating layers of high stress and low stress silicon dioxide, which provide a means of reinforcement of the inorganic dielectric plateau.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Inventors: Jeffrey Alan West, Thomas Dyer Bonifield, Toshiyuki Tamura, Yoshihiro Takei
  • Publication number: 20240113094
    Abstract: A microelectronic device includes a galvanic isolation device on a silicon substrate and a semiconductor device on a semiconductor substrate. The galvanic isolation device includes a lower isolation element over the silicon substrate and an upper isolation element above the lower isolation element, separated by a dielectric plateau that comprises inorganic dielectric material extending from the lower isolation element to the upper isolation element. The galvanic isolation device includes lower bond pads connected to the lower isolation element adjacent to the dielectric plateau, and upper bond pads over the dielectric plateau, connected to the upper isolation element. The semiconductor device includes an active component, and device bond pads coupled to the active component. The microelectronic device includes first electrical connections to the lower bond pads and second electrical connections to the upper bond pads.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Inventors: Jeffrey Alan West, Sreeram N. S., Kashyap Barot, Thomas Dyer Bonifield, Byron Lovell Williams, Elizabeth Costner Stewart
  • Publication number: 20240113155
    Abstract: A microelectronic device includes a galvanic isolation component having a lower isolation element over a substrate with lower bond pads connected to the lower isolation element, a dielectric plateau over the lower isolation element that does not extend to the lower bond pads, and an upper isolation element and upper bond pads over the dielectric plateau. The upper bond pads are laterally separated from the lower bond pads by an isolation distance. The microelectronic device includes high voltage wire bonds on the upper bond pads that extend upward, within 10 degrees of vertical, for a vertical distance greater than the isolation distance. The microelectronic device further includes low voltage wire bonds on the lower bond pads that have a loop height directly over a perimeter of the substrate that is less than 5 times a wire diameter of the low voltage wire bonds.
    Type: Application
    Filed: December 27, 2022
    Publication date: April 4, 2024
    Inventors: Jeffrey Alan West, Hung-Yu Chou, Byron Lovell Williams, Thomas Dyer Bonifield
  • Publication number: 20240112953
    Abstract: A microelectronic device including a galvanic isolator with filler metal within an upper isolation element. The galvanic isolator includes a lower isolation element, an upper isolation element, and an inorganic dielectric plateau between the lower isolation element and the upper isolation element. The upper isolation element contains tines of filler metal which are electrically tied to each other and are electrically tied to the upper isolation element. The ends of the tines are rounded to minimize electric fields. The filler metal increases the overall metal density on the metal layer of the upper isolation element to meet the typical metal density requirements of modern microelectronic fabrication processing.
    Type: Application
    Filed: December 29, 2022
    Publication date: April 4, 2024
    Inventors: Jeffrey Alan West, Elizabeth Costner Stewart, Thomas Dyer Bonifield, Byron Lovell Williams, Kashyap Barot, Viresh Chinchansure, Sreeram N S
  • Patent number: 11942402
    Abstract: An isolator device includes a laminate die having a dielectric laminate material with a metal laminate layer on one side of the dielectric laminate material, the metal laminate layer being a patterned layer providing at least a first plate, including a dielectric layer over the first plate that includes an aperture exposing a portion of the first plate. An integrated circuit (IC) including a substrate having a semiconductor surface includes circuitry including a transmitter and/or a receiver, the IC including a top metal layer providing at least a second plate coupled to a node in the circuitry, with at least one passivation layer on the top metal layer. A non-conductive die attach (NCDA) material for attaching a side of the dielectric laminate material is opposite the metal laminate layer to the IC so that the first plate is at least partially over the second plate to provide a capacitor.
    Type: Grant
    Filed: February 23, 2022
    Date of Patent: March 26, 2024
    Assignee: Texas Instruments Incorporated
    Inventor: Thomas Dyer Bonifield
  • Patent number: 11901402
    Abstract: An electronic device includes a first dielectric layer above a semiconductor layer, lower-bandgap dielectric layer above the first dielectric layer, the lower-bandgap dielectric layer having a bandgap energy less than a bandgap energy of the first dielectric layer, a first capacitor plate above the lower-bandgap dielectric layer in a first plane of first and second directions, a second dielectric layer above the first capacitor plate, a second capacitor plate above the second dielectric layer in a second plane of the first and second directions, the first and second capacitor plates spaced apart from one another along a third direction, and a conductive third capacitor plate above the second dielectric layer in the second plane, the third capacitor plate spaced apart from the second capacitor plate in the second plane.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: February 13, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Elizabeth Costner Stewart, Thomas Dyer Bonifield, Jeffrey Alan West, Byron Lovell Williams
  • Patent number: 11881449
    Abstract: An integrated circuit includes a semiconductor substrate and a plurality of dielectric layers over the semiconductor substrate, including a top dielectric layer. A metal plate or metal coil is located over the top dielectric layer; a metal ring is located over the top dielectric layer and substantially surrounds the metal plate or metal coil. A protective overcoat overlies the metal ring and overlies the metal plate or metal coil. A trench opening is formed through the protective overcoat, with the trench opening exposing the top dielectric layer between the metal plate/coil and the metal ring, the trench opening substantially surrounding the metal plate or metal coil.
    Type: Grant
    Filed: June 30, 2020
    Date of Patent: January 23, 2024
    Assignee: Texas Instruments Incorporated
    Inventors: Jeffrey Alan West, Thomas Dyer Bonifield
  • Publication number: 20230420489
    Abstract: A galvanic isolation capacitor device includes a semiconductor substrate and a PMD layer over the semiconductor substrate. The PMD layer has a first thickness. A lower metal plate is over the PMD layer and an ILD layer is on the lower metal plate; the ILD layer has a second thickness. A ratio of the first thickness to the second thickness is between about 1 and 1.55 inclusive. A first upper metal plate over the ILD layer has a first area and a second upper metal plate over the ILD layer has a second area; a ratio of the first area to the second area is greater than about 5. The galvanic isolation capacitor device can be part of a multi-chip module.
    Type: Application
    Filed: September 6, 2023
    Publication date: December 28, 2023
    Inventors: Thomas Dyer Bonifield, Jeffrey Alan West, Byron Lovell Williams, Elizabeth Costner Stewart
  • Patent number: 11784212
    Abstract: A galvanic isolation capacitor device includes a semiconductor substrate and a PMD layer over the semiconductor substrate. The PMD layer has a first thickness. A lower metal plate is over the PMD layer and an ILD layer is on the lower metal plate; the ILD layer has a second thickness. A ratio of the first thickness to the second thickness is between about 1 and 1.55 inclusive. A first upper metal plate over the ILD layer has a first area and a second upper metal plate over the ILD layer has a second area; a ratio of the first area to the second area is greater than about 5. The galvanic isolation capacitor device can be part of a multi-chip module.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: October 10, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Thomas Dyer Bonifield, Jeffrey Alan West, Byron Lovell Williams, Elizabeth Costner Stewart
  • Publication number: 20230230961
    Abstract: An integrated circuit (IC) package includes a first die with a first surface overlaying a substrate. The first die includes a first metal pad at a second surface opposing the first surface. The IC package also includes a dielectric layer having a first surface contacting the second surface of the first die. The IC package further includes a second die with a surface that contacts a second surface of the dielectric layer. The second die includes a second metal pad aligned with the first metal pad of the first die. A plane perpendicular to the second surface of the first die intersects the first metal pad and the second metal pad.
    Type: Application
    Filed: March 20, 2023
    Publication date: July 20, 2023
    Inventor: THOMAS DYER BONIFIELD
  • Publication number: 20230197634
    Abstract: An integrated circuit with a first conductive region, a second conductive region, a plurality of dielectric layers of a first material type between the first conductive region and the second conductive region, and at least one dielectric layer of a second material type, between a first dielectric layer in the plurality of dielectric layers of a first material type and a second dielectric layer in the plurality of dielectric layers of the first material type. Each dielectric layer of a first material type has a thickness in a range from 0.5 ?m to 5.0 ?m, and the at least one dielectric layer of a second material type is not contacting a metal and has a thickness less than 2.0 ?m, and the second material type differs from the first material type in at least one of compression stress or elements in the first material type as compared to elements in the second material type.
    Type: Application
    Filed: December 21, 2021
    Publication date: June 22, 2023
    Inventors: Elizabeth Costner Stewart, Jeffrey Alan West, Thomas Dyer Bonifield
  • Publication number: 20230154974
    Abstract: An electronic device includes a first dielectric layer above a semiconductor layer, lower-bandgap dielectric layer above the first dielectric layer, the lower-bandgap dielectric layer having a bandgap energy less than a bandgap energy of the first dielectric layer, a first capacitor plate above the lower-bandgap dielectric layer in a first plane of first and second directions, a second dielectric layer above the first capacitor plate, a second capacitor plate above the second dielectric layer in a second plane of the first and second directions, the first and second capacitor plates spaced apart from one another along a third direction, and a conductive third capacitor plate above the second dielectric layer in the second plane, the third capacitor plate spaced apart from the second capacitor plate in the second plane.
    Type: Application
    Filed: November 18, 2021
    Publication date: May 18, 2023
    Inventors: Elizabeth Costner Stewart, Thomas Dyer Bonifield, Jeffrey Alan West, Byron Lovell Williams
  • Publication number: 20230138570
    Abstract: In examples, a semiconductor package comprises a first driver die adapted to be coupled to a high-side switch of a power supply, the first driver die adapted to drive a gate of the high-side switch. The package also includes a second driver die adapted to be coupled to a low-side switch of the power supply, the second driver die adapted to drive a gate of the low-side switch. The package also includes a controller die positioned between the first and second driver dies and configured to control the first and second driver dies. The package also includes a pair of bond wires configured to provide a differential signal between the controller die and the first driver die, a vertical plane of a bond wire in the pair of bond wires and a vertical plane of a side surface of the first driver die having an angle therebetween ranging from 80 to 95 degrees.
    Type: Application
    Filed: October 29, 2021
    Publication date: May 4, 2023
    Inventors: Thomas Dyer BONIFIELD, Sarvesh Jagdish BANG, Chittranjan Mohan GUPTA
  • Publication number: 20230129759
    Abstract: This description relates generally to semiconductor devices. A semiconductor device can include first and second conductive layers that can be positioned over a substrate, and at least one dielectric layer between the first and second conductive layers. The at least one dielectric layer can be positioned over at least a portion of the second conductive layer, and the first conductive layer can be positioned over a portion of the least one dielectric layer. The semiconductor device can further include a third conductive layer that can be positioned over the substrate and can be conductively connected to the second conductive layer and the substrate. The third conductive layer includes a fusible link.
    Type: Application
    Filed: October 27, 2021
    Publication date: April 27, 2023
    Inventors: HONGLIN GUO, THOMAS DYER BONIFIELD
  • Patent number: 11616048
    Abstract: An integrated circuit (IC) package includes a first die with a first surface overlaying a substrate. The first die includes a first metal pad at a second surface opposing the first surface. The IC package also includes a dielectric layer having a first surface contacting the second surface of the first die. The IC package further includes a second die with a surface that contacts a second surface of the dielectric layer. The second die includes a second metal pad aligned with the first metal pad of the first die. A plane perpendicular to the second surface of the first die intersects the first metal pad and the second metal pad.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: March 28, 2023
    Assignee: Texas Instruments Incorporated
    Inventor: Thomas Dyer Bonifield
  • Publication number: 20230056046
    Abstract: An electronic device has a conductive shield between first and second regions in a multilevel metallization structure, as well as a capacitor with first and second terminals in the first region, the first terminal laterally overlaps the second terminal by an overlap distance of 1.0 ?m to 6.0 ?m, the conductive shield includes a first metal line that encircles the first terminal, and the first metal line is spaced apart from the first terminal by a gap distance of 0.5 ?m to 1.0 ?m.
    Type: Application
    Filed: February 28, 2022
    Publication date: February 23, 2023
    Inventors: Byron Lovell Williams, Elizabeth Costner Stewart, Jeffrey Alan West, Thomas Dyer Bonifield
  • Publication number: 20230047044
    Abstract: A microelectronic device includes a semiconductor substrate and a high voltage isolation capacitor over the substrate. The capacitor includes a bottom capacitor plate over the substrate. Dielectric layers are formed above the bottom capacitor plate, including a top dielectric layer. A high dielectric layer on the top dielectric layer includes at least a first sublayer having a first dielectric constant that is higher than a dielectric constant of the top dielectric layer. A top capacitor plate is formed on the high dielectric layer over the bottom capacitor plate. An electric field abatement structure surrounds the top capacitor plate. The electric field abatement structure includes a shelf of the high dielectric layer extending outward from a lower corner of the bottom capacitor plate at least 14 microns, and an isolation break in the high dielectric layer past the shelf, in which the first sublayer is removed from the isolation break.
    Type: Application
    Filed: August 16, 2021
    Publication date: February 16, 2023
    Inventors: Elizabeth Stewart Costner, Jeffrey Alan West, Thomas Dyer Bonifield