Abstract: A computer-implemented method of controlling power consumption in a multi-processor computing device, the method comprises: determining a target sound level for the multi-processor computing device; determining one or more candidate fan speed combinations for a first fan associated with a first temperature-controlled device included in the multi-processor computing device and a second fan associated with a second temperature-controlled device included in the multi-processor computing device based on the target sound level; determining a temperature error for one of the first temperature-controlled device, the second temperature-controlled device, or a third temperature-controlled device included in the multi-processor computing device based on the one or more candidate fan speed combinations and a measured temperature value for one of the first temperature-controlled device, the second temperature-controlled device, or the third temperature-controlled device; determining a value for a first power setting asso

Abstract: A computer-implemented method of controlling power consumption in a multi-processor computing device comprises determining a first value for a first power setting associated with a first processor based on a sound level generated by the multi-processor computing device; determining a second value for the first power setting based on a power consumption level of the multi-processor computing device; comparing the first value to the second value; and causing the first processor to perform one or more operations based on the lesser of the first value and the second value.

Abstract: Various embodiments include techniques for controlling temperature and fan speed in a computing system. Conventional computing systems present the user with a very limited set of three or four curated performance mode presets, which can impose substantial trade-offs in performance, acoustic noise, and/or case temperature that the user may find to be unacceptable. By contrast, the disclosed techniques allow the user to precisely position the operation of the computing system anywhere in the two-dimensional space of fan speed (which determines acoustic noise) versus case temperature that suits the preference of the user. The disclosed techniques further provide a closed-loop feedback control system for controlling the case temperature. This closed-loop feedback control system operates in conjunction with the adjustable case temperature target to determine individual power limits for certain components, such as a CPU power limit, a GPU power limit, and/or the like.

Abstract: A computer-implemented method of controlling power consumption in a multi-processor computing device comprises: determining whether a first processor is operating in a high-power regime or a low-power regime; selecting a first set of control rules that includes a first subset of control rules that apply when the first processor is operating in the high-power regime and a second subset of control rules that apply when the first processor is operating in the low-power regime; determining one or more power settings for the first processor based on the first set of control rules; and causing the first processor to perform one or more operations based on the one or more power settings.

Abstract: A computer-implemented method of controlling power consumption in a multi-processor computing device comprises: determining whether a first processor is operating in a high-power regime or a low-power regime; selecting a first set of control rules that includes a first subset of control rules that apply when the first processor is operating in the high-power regime and a second subset of control rules that apply when the first processor is operating in the low-power regime; determining one or more power settings for the first processor based on the first set of control rules; and causing the first processor to perform one or more operations based on the one or more power settings.

Abstract: An optimized power saving technique is described for a processor, such as, for example, a graphic processing unit (GPU), which includes one or more processing cores and at least one data link interface. According to the technique, the processor is operable in a low power mode in which power to the at least one processing core is off and power to the at least one data link interface is on. This technique provides reduced exit latencies compared to currently available approaches in which the core power is turned off.

Abstract: A method for managing power in a multiple processor computing device includes detecting a first amount of power being used by a first processor of the computing device; determining an amount of extra power available based on the first amount of power and a power budget for the first processor; and transmits a value to a driver associated with a second processor of the computing device, wherein the value indicates the amount of extra power available, wherein the driver adjusts at least one operating parameter of the second processor based on the amount of extra power available.

Abstract: A computer-implemented method of controlling power consumption in a multi-processor computing device, the method comprises: determining a target sound level for the multi-processor computing device; determining one or more candidate fan speed combinations for a first fan associated with a first temperature-controlled device included in the multi-processor computing device and a second fan associated with a second temperature-controlled device included in the multi-processor computing device based on the target sound level; determining a temperature error for one of the first temperature-controlled device, the second temperature-controlled device, or a third temperature-controlled device included in the multi-processor computing device based on the one or more candidate fan speed combinations and a measured temperature value for one of the first temperature-controlled device, the second temperature-controlled device, or the third temperature-controlled device; determining a value for a first power setting asso

Abstract: A computer-implemented method of controlling power consumption in a multi-processor computing device comprises: determining whether a first processor is operating in a high-power regime or a low-power regime; selecting a first set of control rules that includes a first subset of control rules that apply when the first processor is operating in the high-power regime and a second subset of control rules that apply when the first processor is operating in the low-power regime; determining one or more power settings for the first processor based on the first set of control rules; and causing the first processor to perform one or more operations based on the one or more power settings.

Abstract: A computer-implemented method of controlling power consumption in a multi-processor computing device comprises determining a first value for a first power setting associated with a first processor based on a sound level generated by the multi-processor computing device; determining a second value for the first power setting based on a power consumption level of the multi-processor computing device; comparing the first value to the second value; and causing the first processor to perform one or more operations based on the lesser of the first value and the second value.

Abstract: A method for managing power in a multiple processor computing device includes detecting a first amount of power being used by a first processor of the computing device; determining an amount of extra power available based on the first amount of power and a power budget for the first processor; and transmits a value to a driver associated with a second processor of the computing device, wherein the value indicates the amount of extra power available, wherein the driver adjusts at least one operating parameter of the second processor based on the amount of extra power available.

Abstract: A method for managing power in a multiple processor computing device includes detecting a first amount of power being used by a first processor of the computing device; determining an amount of extra power available based on the first amount of power and a power budget for the first processor; and transmits a value to a driver associated with a second processor of the computing device, wherein the value indicates the amount of extra power available, wherein the driver adjusts at least one operating parameter of the second processor based on the amount of extra power available.

Abstract: An integrated circuit such as, for example a graphics processing unit (GPU), having an on-chip analog to digital converter (ADC) for use in overcurrent protection of the chip is described, where the overcurrent protection response times are substantially faster than techniques with external ADC. A system-on-chip (SoC) includes the integrated circuit and a multiplexer arranged externally to the chip having the ADC, where the multiplexer provides the ADC with a data stream of sampling information from a plurality of power sources. Methods for overcurrent protection using an on-chip ADC are also described.

Abstract: A technique is disclosed for a graphics processing unit (GPU) to enter and exit a power saving deep sleep mode. The technique involves preserving processing state within local memory by configuring the local memory to operate in a self-refresh mode while the GPU is powered off for deep sleep. An interface circuit coupled to the local memory is configured to prevent spurious GPU signals from disrupting proper self-refresh of the local memory. Spurious GPU signals may result from GPU power down and GPU power up events associated with the GPU entering and exiting the deep sleep mode.

Abstract: A method for managing power in a multiple processor computing device includes detecting a first amount of power being used by a first processor of the computing device; determining an amount of extra power available based on the first amount of power and a power budget for the first processor; and transmits a value to a driver associated with a second processor of the computing device, wherein the value indicates the amount of extra power available, wherein the driver adjusts at least one operating parameter of the second processor based on the amount of extra power available.

Abstract: An integrated circuit such as, for example a graphics processing unit (GPU), having an on-chip analog to digital converter (ADC) for use in overcurrent protection of the chip is described, where the overcurrent protection response times are substantially faster than techniques with external ADC. A system-on-chip (SoC) includes the integrated circuit and a multiplexer arranged externally to the chip having the ADC, where the multiplexer provides the ADC with a data stream of sampling information from a plurality of power sources. Methods for overcurrent protection using an on-chip ADC are also described.

Abstract: An optimized power saving technique is described for a processor, such as, for example, a graphic processing unit (GPU), which includes one or more processing cores and at least one data link interface. According to the technique, the processor is operable in a low power mode in which power to the at least one processing core is off and power to the at least one data link interface is on. This technique provides reduced exit latencies compared to currently available approaches in which the core power is turned off.

Abstract: An optimized power saving technique is described for a processor, such as, for example, a graphic processing unit (GPU), which includes one or more processing cores and at least one data link interface. According to the technique, the processor is operable in a low power mode in which power to the at least one processing core is off and power to the at least one data link interface is on. This technique provides reduced exit latencies compared to currently available approaches in which the core power is turned off.

Abstract: A method and apparatus for performing display image refresh in bursts to a display device. A buffered refresh controller includes capabilities to drive the display based on video signals generated from a local frame buffer at a first rate. The graphics controller may optimally be configured to burst a new frame of pixel data to the buffered refresh controller at a second rate to replace the previous frame of pixel data in the local frame buffer. The second rate is different than the first rate. Additionally, the graphics controller may send frames only when they contain new pixel data. By enabling the graphics controller to selectively transmit the new frame of pixel data at the second rate, higher than the first rate, the graphics controller may be placed in a power-saving state during at least a portion of each frame update.

Abstract: A method and apparatus for supporting a self-refreshing display device coupled to a graphics controller are disclosed. A technique for setting the operating state of the graphics controller during initialization from a deep sleep state is described. The graphics controller may set the operating state based on a signal that controls whether the graphics controller executes a warm-boot initialization procedure or a cold-boot initialization procedure. In the warm-boot initialization procedure, instructions and values stored in a non-volatile memory connected to the graphics controller may be used to set the operating state of the graphics controller. In one embodiment, the graphics controller may determine whether any changes have been made to the physical configuration of the computer system and, if the physical configuration has changed, the graphics controller may set the operating state based on values received from a software driver.