Abstract: Devices and methods for a microLED array and a bonded CMOS driver chip. An example array includes a plurality of microLEDs having backside contacts, a plurality of through-substrate vias, a CMOS driver chip bonded to the backside contacts of the microLEDs, and an encapsulating layer forming an integrated surface of the array. At least one through-substrate via is paired with each microLED. Each through-substrate via electrically connects the paired microLED to the CMOS driver chip.

Abstract: Devices and methods for analyzing polymer arrays formed on integrated surfaces of microLEDs. One microarray includes a plurality of individually controllable microLED elements, a plurality of photodetector elements, an integrated surface, and a CMOS driver chip. Each microLED element is paired with a photodetector element. The CMOS driver chip controls activation of the microLED elements and the photodetector elements.

Abstract: In accordance with the present invention, a method, system, computer system, and computer program product for considering clock skew in designing digital systems with latch-controlled circuits are provided. The disclosure teaches a method for determining whether logic operations can be performed within the available time and allows detailed modeling of clock skew for different domains of the integrated circuit. Taking clock skew into account for each domain, worst-case timing paths can be determined for circuits controlled by either flip-flops or latches. A design of an integrated circuit can be revised or verified using the method taught. The disclosure envisions that integrated circuits, printed circuit boards, computer systems and other components will be manufactured based upon designs developed with the method taught.

Abstract: In accordance with the present invention, a method, system, computer system, and computer program product for considering clock skew in designing digital systems with latch-controlled circuits are provided. The disclosure teaches a method for determining whether logic operations can be performed within the available time and allows detailed modeling of clock skew for different domains of the integrated circuit. Taking clock skew into account for each domain, worst-case timing paths can be determined for circuits controlled by either flip-flops or latches. A design of an integrated circuit can be revised or verified using the method taught. The disclosure envisions that integrated circuits, printed circuit boards, computer systems and other components will be manufactured based upon designs developed with the method taught.

Abstract: A regulated on-chip substrate-voltage generator circuit converts a single power supply input and ground potential into a negative potential. The negative potential is applied to the substrate of an integrated circuit upon which the substrate-voltage generator is formed. The substrate voltage generator includes a voltage oscillator connected to a charge pump device. A pair of depletion FETs forms a voltage divider circuit between the ground potential and the substrate potential. An amplifier, formed from depletion FETs, couples the voltage divider into the charge pump. The voltage divider and amplifier regulate the charge pump thereby maintaining tight control over the substrate voltage.