Patents by Inventor Thomas E. Doane
Thomas E. Doane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9499920Abstract: A method of producing rectangular seeds for use in semiconductor or solar material manufacturing includes connecting an adhesive layer to a top surface of a template, the template including a plurality of parallel slots, and drawing alignment lines on the adhesive layer, the alignment lines aligned with at least some of the parallel slots. The method also includes connecting quarter sections to the adhesive layer such that an interface between a rectangular seed portion and a curved wing portion of each quarter section is aligned with at least one of the alignment lines drawn on the adhesive layer, and slicing each of the quarter sections to separate the rectangular seed portions from the curved wing portions.Type: GrantFiled: July 9, 2015Date of Patent: November 22, 2016Assignee: MEMC Singapore Pte. Ltd. (UEN200614794D)Inventors: Jihong John Chen, Susan S. Dwyer, Shawn Wesley Hayes, Thomas E. Doane, Dale A. Witte, Linda K. Swiney, Travis L. Hambach
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Publication number: 20150308011Abstract: A method of producing rectangular seeds for use in semiconductor or solar material manufacturing includes connecting an adhesive layer to a top surface of a template, the template including a plurality of parallel slots, and drawing alignment lines on the adhesive layer, the alignment lines aligned with at least some of the parallel slots. The method also includes connecting quarter sections to the adhesive layer such that an interface between a rectangular seed portion and a curved wing portion of each quarter section is aligned with at least one of the alignment lines drawn on the adhesive layer, and slicing each of the quarter sections to separate the rectangular seed portions from the curved wing portions.Type: ApplicationFiled: July 9, 2015Publication date: October 29, 2015Inventors: Jihong John Chen, Susan S. Dwyer, Shawn Wesley Hayes, Thomas E. Doane, Dale A. Witte, Linda K. Swiney, Travis L. Hambach
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Patent number: 9136185Abstract: Methods and systems for evaluation of wafers are disclosed. One example method includes illuminating a multi-crystalline wafer according to a plurality of lighting parameters, capturing a plurality of images of the multi-crystalline wafer, stacking and projecting the plurality of images to generate a composite image, analyzing the composite image to identify one or more grains of the multi-crystalline wafer, and generating a report based on the analysis of the composite image. The multi-crystalline wafer is illuminated according to a different one of the plurality of lighting parameters in at least two of the plurality of images.Type: GrantFiled: December 19, 2011Date of Patent: September 15, 2015Assignee: MEMC Singapore Pte., Ltd.Inventors: Gang Shi, Thomas E. Doane, Steven L. Kimbel, Robert H. Fuerhoff
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Patent number: 9111745Abstract: A method of producing rectangular seeds for use in semiconductor or solar material manufacturing includes connecting an adhesive layer to a top surface of a template, the template including a plurality of parallel slots, and drawing alignment lines on the adhesive layer, the alignment lines aligned with at least some of the parallel slots. The method also includes connecting quarter sections to the alignment layer such that an interface between a rectangular seed portion and a curved wing portion of each quarter section is aligned with at least one of the alignment lines drawn on the adhesive layer, and slicing each of the quarter sections to separate the rectangular seed portions from the curved wing portions.Type: GrantFiled: December 31, 2012Date of Patent: August 18, 2015Assignee: MEMC Singapore Pte., Ltd. (UEN200614794D)Inventors: Jihong John Chen, Susan S. Dwyer, Shawn Wesley Hayes, Thomas E. Doane, Dale A. Witte, Linda K. Swiney, Travis L. Hambach
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Publication number: 20130156293Abstract: Methods and systems for evaluation of wafers are disclosed. One example method includes illuminating a multi-crystalline wafer according to a plurality of lighting parameters, capturing a plurality of images of the multi-crystalline wafer, stacking and projecting the plurality of images to generate a composite image, analyzing the composite image to identify one or more grains of the multi-crystalline wafer, and generating a report based on the analysis of the composite image. The multi-crystalline wafer is illuminated according to a different one of the plurality of lighting parameters in at least two of the plurality of images.Type: ApplicationFiled: December 19, 2011Publication date: June 20, 2013Applicant: MEMC Singapore, Pte. Ltd.(UEN200614794D)Inventors: Gang Shi, Thomas E. Doane, Steven L. Kimbel, Robert H. Fuerhoff
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Patent number: 8309464Abstract: The present disclosure generally relates to the manufacture of silicon wafers, and more particularly to edge etching apparatus and methods for etching the edge of a silicon wafer.Type: GrantFiled: March 31, 2009Date of Patent: November 13, 2012Assignee: MEMC Electronic Materials, Inc.Inventors: Henry F. Erk, Peter D. Albrecht, Eugene R. Hollander, Thomas E. Doane, Judith A. Schmidt, Roland R. Vandamme, Guoqiang (David) Zhang
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Patent number: 8192822Abstract: The present disclosure generally relates to the manufacture of silicon wafers, and more particularly to edge etching apparatus and methods for etching the edge of a silicon wafer.Type: GrantFiled: March 31, 2009Date of Patent: June 5, 2012Assignee: MEMC Electronic Materials, Inc.Inventors: Henry F. Erk, Peter D. Albrecht, Eugene R. Hollander, Thomas E. Doane, Judith A. Schmidt, Roland R. Vandamme, Guoqiang (David) Zhang
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Publication number: 20090247055Abstract: The present disclosure generally relates to the manufacture of silicon wafers, and more particularly to edge etching apparatus and methods for etching the edge of a silicon wafer.Type: ApplicationFiled: March 31, 2009Publication date: October 1, 2009Applicant: MEMC ELECTRONIC MATERIALS, INC.Inventors: Henry F. Erk, Peter D. Albrecht, Eugene R. Hollander, Thomas E. Doane, Judith A. Schmidt, Roland R. Vandamme, Guoqiang (David) Zhang
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Publication number: 20090242126Abstract: The present disclosure generally relates to the manufacture of silicon wafers, and more particularly to edge etching apparatus and methods for etching the edge of a silicon wafer.Type: ApplicationFiled: March 31, 2009Publication date: October 1, 2009Applicant: MEMC ELECTRONIC MATERIALS, INC.Inventors: Henry F. Erk, Peter D. Albrecht, Eugene R. Hollander, Thomas E. Doane, Judith A. Schmidt, Roland Vandamme, Guoqiang (David) Zhang
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Publication number: 20090246444Abstract: The present disclosure generally relates to the manufacture of silicon wafers, and more particularly to edge etching apparatus and methods for etching the edge of a silicon wafer.Type: ApplicationFiled: March 31, 2009Publication date: October 1, 2009Applicant: MEMC ELECTRONIC MATERIALS, INC.Inventors: Henry F. Erk, Peter D. Albrecht, Eugene R. Hollander, Thomas E. Doane, Judith A. Schmidt, Roland R. Vandamme, Guoqiang (David) Zhang
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Patent number: 7323421Abstract: A process for etching silicon wafers using a caustic etchant in the form of an aqueous solution comprising water, a hydroxide ion source, and a chelating agent. The process produces silicon wafers substantially free from diffused metal ions.Type: GrantFiled: June 14, 2005Date of Patent: January 29, 2008Assignee: MEMC Electronic Materials, Inc.Inventors: Mark G. Stinson, Henry F. Erk, Guoqiang (David) Zhang, Mick Bjelopavlic, Alexis Grabbe, Jozef G. Vermeire, Judith A. Schmidt, Thomas E. Doane, James R. Capstick
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Publication number: 20040108297Abstract: A process for etching silicon wafers using a caustic etchant in the form of an aqueous solution comprising water and a source of hydroxide ions and generally characterized by a lower concentration of water and/or higher concentration of source of hydroxide ions. In accordance with another embodiment, the caustic etchant includes a salt additive. The process produces silicon wafers with improved surface characteristics such as flatness and nanotopography.Type: ApplicationFiled: September 18, 2003Publication date: June 10, 2004Applicant: MEMC Electronic Materials, Inc.Inventors: Henry F. Erk, James R. Capstick, Thomas E. Doane, Alexis Grabbe, Judith A. Schmidt, Annlie Sing, Mark G. Stinson, Guoqiang (David) Zhang
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Publication number: 20020142619Abstract: A process for etching a silicon wafer is disclosed. The process comprises oxidizing silicon with permanganate ions and stripping the silicon oxide with hydrofluoric acid, in the presence of a non-oxidizable acid and typically a surfactant. The present process affords a means to more consistently obtain a silicon wafer having improved gloss or smoothness, while minimizing both the amount of silicon removed from the wafer surface and the cost of the etching process.Type: ApplicationFiled: January 4, 2002Publication date: October 3, 2002Applicant: MEMC Electronic Materials, Inc.Inventors: Alexis Grabbe, Thomas E. Doane