Abstract: A method of outputting data from a FIFO incorporated in an integrated circuit generally determines whether input data is valid during a first clock cycle. The method then outputs data from a plurality of output barrel slots during a second clock cycle. Data is then shifted from predetermined upper barrel slots to predetermined output barrel slots during second cycle based upon a barrel count. Finally, data is shifted into the FIFO during said second cycle based upon the barrel count. A new barrel count of valid data in the FIFO can then be determined. Circuitry for implementing the embodiments of the invention is also disclosed.

Abstract: A blockRAM based FIFO utilizes the blockRAM components to implement a one-cycle latency read FIFO. This FIFO implementation, while utilizing blockRAM, provides fast clock to out times by registering all data in a register prior to presenting it to the user. Because this implementation transparently registers the data, the user interface remains identical to conventional FIFO implementations, while solving the slow clock-to-out time associated with blockRAM based FIFOs. A blockRAM based zero-cycle latency read FIFO is also described.