Abstract: An apparatus which allows for software sharing between multiple controllers includes a computer bus and a plurality of processors each having input and output ports coupled to the bus. Each processor also has at least one internal storage register. The apparatus further includes means, which are responsive to a signal indicating which one of the plurality of processors is controlling the computer bus and to a portion of address data on the bus, for issuing a control signal to one of the plurality of processors to permit that one processor access to at least one of its internal storage register when that processor issues a bus access request having an address which is within the range of addresses of all the processors.

Abstract: A system and method for testing a computing system by introducing stall cycles at an arbiter that controls access to a bus that is commonly used by the CPU and I/O devices for stressing the computing system with regard to the latency and bandwidth.

Abstract: Apparatus for sharing data between processors having certain incompatible data formats is provided. A configurable data path unit and an address mapping unit allow a peripheral processor to access addressable storage locations within a host processor's main memory and store data types in a format so that the both processors can correctly access and interpret the data.

Abstract: Firmware resident in electrically erasable programmable read only memory ("EEPROM") can be updated by a user while maintaining the intelligence of a computer system during the updating process by a control logic device. The control logic device decodes address and control signals to provide a hardware partitioning of the firmware resident in the EEPROMs to prevent writing to protected partitions of the firmware. Transfer vectors are used to provide indirect accessing of subroutines resident in the firmware. During an updating process, a new version of a subroutine is stored in a free area in the EEPROMs before the transfer vector pointing to the old version of the subroutine is updated. The window of vulnerability to errors during the updating process is minimized by only updating a page of memory containing the transfer vector that points to the old version of the subroutine after the new version has been stored.