Abstract: In some embodiments, connecting a component to a substrate by adhesion to an oxidized solder surface includes: forming one or more conductive solder connections between the component and one or more conductive portions of the substrate; adhering the component to an oxidized surface of a solder portion applied to the substrate.

Abstract: Multiple integrated circuit (IC) devices are connected to a top side metallization surface of a multi IC device carrier. The carrier includes resin based substrate layers and associated wiring line layers. To reduce stain of the resin layers, especially in region(s) within the carrier between the IC devices, a stiffener or stiffeners are applied to the back side metallization (BSM) surface of the IC device carrier. The stiffener(s) reduce the amount of curvature of the IC device carrier and reduce the strain seen by the resin layer(s), thereby mitigating the risk for cracks forming and expanding within the resin layers.

Abstract: A method of managing thermal warpage of a laminate which includes: assembling a stiffener and an adhesive on the laminate, the stiffener being a material that has a higher modulus of elasticity than the laminate; applying a force to deform the laminate a predetermined amount; heating the laminate, stiffener and adhesive to a predetermined temperature at which the adhesive cures to bond the stiffener to the laminate; cooling the laminate, stiffener and adhesive to a temperature below the predetermined temperature, the laminate maintaining its deformed shape.

Abstract: Multiple integrated circuit (IC) devices are connected to a top side metallization surface of a multi IC device carrier. The carrier includes resin based substrate layers and associated wiring line layers. To reduce stain of the resin layers, especially in region(s) within the carrier between the IC devices, a stiffener or stiffeners are applied to the back side metallization (BSM) surface of the IC device carrier. The stiffener(s) reduce the amount of curvature of the IC device carrier and reduce the strain seen by the resin layer(s), thereby mitigating the risk for cracks forming and expanding within the resin layers.

Abstract: An interconnect structure that includes a component circuit board containing a plurality of electrical components, and a wafer connector assembly. The wafer connector assembly includes a plurality of interconnect circuit boards that are in electrical connection with the components circuit board through a plurality of rows of solder joints, the plurality of interconnect circuit boards having a connection end including at least one contact. An adhesive is present structurally reinforcing at least a row of the solder joints that is proximate to the connection end of the plurality of interconnect circuit boards of the wafer assembly.

Abstract: A method of managing thermal warpage of a laminate which includes: assembling a stiffener and an adhesive on the laminate, the stiffener being a material that has a higher modulus of elasticity than the laminate; applying a force to deform the laminate a predetermined amount; heating the laminate, stiffener and adhesive to a predetermined temperature at which the adhesive cures to bond the stiffener to the laminate; cooling the laminate, stiffener and adhesive to a temperature below the predetermined temperature, the laminate maintaining its deformed shape.

Abstract: An interconnect structure that includes a component circuit board containing a plurality of electrical components, and a wafer connector assembly. The wafer connector assembly includes a plurality of interconnect circuit boards that are in electrical connection with the components circuit board through a plurality of rows of solder joints, the plurality of interconnect circuit boards having a connection end including at least one contact. An adhesive is present structurally reinforcing at least a row of the solder joints that is proximate to the connection end of the plurality of interconnect circuit boards of the wafer assembly.

Abstract: An interconnect structure that includes a component circuit board containing a plurality of electrical components, and a wafer connector assembly. The wafer connector assembly includes a plurality of interconnect circuit boards that are in electrical connection with the components circuit board through a plurality of rows of solder joints, the plurality of interconnect circuit boards having a connection end including at least one contact. An adhesive is present structurally reinforcing at least a row of the solder joints that is proximate to the connection end of the plurality of interconnect circuit boards of the wafer assembly.

Abstract: An interconnect structure that includes a component circuit board containing a plurality of electrical components, and a wafer connector assembly. The wafer connector assembly includes a plurality of interconnect circuit boards that are in electrical connection with the components circuit board through a plurality of rows of solder joints, the plurality of interconnect circuit boards having a connection end including at least one contact. An adhesive is present structurally reinforcing at least a row of the solder joints that is proximate to the connection end of the plurality of interconnect circuit boards of the wafer assembly.

Abstract: A fixture assembly and method of forming a chip assembly is provided. The fixture assembly includes a first plate having an opening sized to accommodate a chip mounted on a laminate. The fixture assembly further includes a second plate mated to the first plate by at least one mechanical fastening mechanism. The fixture assembly further includes a space defined by facing surfaces of the first plate and the second plate and confined by a raised stepped portion of at least one of the first plate and the second plate. The space is coincident with the opening. The space is sized and shaped such that the laminate is confined within the space and directly abuts the stepped portion and the facing surfaces of the first plate and the second plate to be confined in X, Y and Z directions.

Abstract: An interconnect structure that includes a component circuit board containing a plurality of electrical components, and a wafer connector assembly. The wafer connector assembly includes a plurality of interconnect circuit boards that are in electrical connection with the components circuit board through a plurality of rows of solder joints, the plurality of interconnect circuit boards having a connection end including at least one contact. An adhesive is present structurally reinforcing at least a row of the solder joints that is proximate to the connection end of the plurality of interconnect circuit boards of the wafer assembly.

Abstract: A method includes applying flux solution during a soldering process. Metal ions are dissolved into the flux solution as a result of the soldering process. The method also includes rinsing the flux solution with a first rinse solution. The first rinse solution includes organic and/or sulfur species, and the organic and/or sulfur species stabilize the metal ions that are dissolved in the flux solution.

Abstract: The disclosure relates to semiconductor structures and, more particularly, to barrier structures for underfill blockout regions uses in phonotics chip packaging and methods of manufacture. The structure includes a substrate with a plurality of solder connections and at least one optical fiber interface disposed within at least one cavity of the substrate. The structure further includes a barrier structure formed about the cavity which is structured to prevent underfill material from degrading an optical coupling of the optical fiber.

Abstract: An interconnect structure that includes a component circuit board containing a plurality of electrical components, and a wafer connector assembly. The wafer connector assembly includes a plurality of interconnect circuit boards that are in electrical connection with the components circuit board through a plurality of rows of solder joints, the plurality of interconnect circuit boards having a connection end including at least one contact. An adhesive is present structurally reinforcing at least a row of the solder joints that is proximate to the connection end of the plurality of interconnect circuit boards of the wafer assembly.

Abstract: A technique relates to forming a chip assembly. Top and bottom chip stack elements containing solder pads and a solder material are provided. Soluble standoffs are applied to the bottom chip stack element. The chip stack elements are aligned to bring the top solder pad in proximity to the bottom solder pad and the temperature is raised to a temperature above the melting temperature of the solder material to form a connected chip assembly. The connected chip assembly is cooled to re-solidify the solder material and soluble standoffs are removed from the connected chip assembly.

Abstract: A technique relates to forming a chip assembly. Top and bottom chip stack elements containing solder pads and a solder material are provided. Soluble standoffs are applied to the bottom chip stack element. The chip stack elements are aligned to bring the top solder pad in proximity to the bottom solder pad and the temperature is raised to a temperature above the melting temperature of the solder material to form a connected chip assembly. The connected chip assembly is cooled to re-solidify the solder material and soluble standoffs are removed from the connected chip assembly.

Abstract: The disclosure relates to semiconductor structures and, more particularly, to barrier structures for underfill blockout regions uses in phonotics chip packaging and methods of manufacture. The structure includes a substrate with a plurality of solder connections and at least one optical fiber interface disposed within at least one cavity of the substrate. The structure further includes a barrier structure formed about the cavity which is structured to prevent underfill material from degrading an optical coupling of the optical fiber.

Abstract: An interconnect structure that includes a component circuit board containing a plurality of electrical components, and a wafer connector assembly. The wafer connector assembly includes a plurality of interconnect circuit boards that are in electrical connection with the components circuit board through a plurality of rows of solder joints, the plurality of interconnect circuit boards having a connection end including at least one contact. An adhesive is present structurally reinforcing at least a row of the solder joints that is proximate to the connection end of the plurality of interconnect circuit boards of the wafer assembly.

Abstract: A method including providing a laminate substrate, characterizing the laminate substrate for warpage characteristics, determining a horizontal plane distortion based on the warpage characteristics, and placing the laminate substrate into a fixture with an adjustment to correct the horizontal plane distortion, the adjustment being located in a center of the laminate substrate, wherein the adjustment contacts the laminate substrate. The method may further include fluxing the laminate substrate, placing a chip onto the laminate substrate, and placing the fixture into a reflow furnace to join the chip and the laminate substrate.

Abstract: A fixture assembly and method of forming a chip assembly is provided. The fixture assembly includes a first plate having an opening sized to accommodate a chip mounted on a laminate. The fixture assembly further includes a second plate mated to the first plate by at least one mechanical fastening mechanism. The fixture assembly further includes a space defined by facing surfaces of the first plate and the second plate and confined by a raised stepped portion of at least one of the first plate and the second plate. The space is coincident with the opening. The space is sized and shaped such that the laminate is confined within the space and directly abuts the stepped portion and the facing surfaces of the first plate and the second plate to be confined in X, Y and Z directions.