Patents by Inventor Thomas E. Nagle

Thomas E. Nagle has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6191021
    Abstract: Generally, and in one form of the invention, a method is disclosed for forming an ohmic contact on a GaAs surface 20 comprising the steps of depositing a layer of InGaAs 22 over the GaAs surface 20, and depositing a layer of TiW 24 on the layer of InGaAs 22, whereby a reliable and stable electrical contact is established to the GaAs surface 20 and whereby Ti does not generally react with the In.
    Type: Grant
    Filed: April 23, 1997
    Date of Patent: February 20, 2001
    Assignee: TriQuint Semiconductors Texas, Inc.
    Inventors: Clyde R. Fuller, Joseph B. Delaney, Thomas E. Nagle
  • Patent number: 5804877
    Abstract: Generally, and in one form of the invention, a method is disclosed for forming an ohmic contact on a GaAs surface 20 comprising the steps of depositing a layer of InGaAs 22 over the GaAs surface 20, and depositing a layer of TiW 24 on the layer of InGaAs 22, whereby a reliable and stable electrical contact is established to the GaAs surface 20 and whereby Ti does not generally react with the In.
    Type: Grant
    Filed: June 20, 1996
    Date of Patent: September 8, 1998
    Assignee: Texas Instruments Incorporated
    Inventors: Clyde R. Fuller, Joseph B. Delaney, Thomas E. Nagle
  • Patent number: 5537284
    Abstract: In one form of the invention, an Electrostatic Discharge protection device containing at least one heterojunction transistor is disclosed. In another embodiment, an Electrostatic Discharge protection circuit comprises: a first terminal contact 20; an NPN heterojunction bipolar transistor Q2; a PNP bipolar transistor Q1; a base-emitter shunt resistor R2; an emitter of said PNP transistor connected to said first terminal contact; a base of said PNP transistor connected to collector of said NPN transistor; a collector of said PNP transistor connected to a base of said NPN transistor; and an emitter of said NPN transistor connected to a second terminal contact 22, with said base-emitter shunt resistor connected between said base of said NPN transistor and an emitter of said NPN transistor, whereby a low-capacitance device capable of protecting semiconductor devices from electrostatic discharges in excess of 4000 Volts results. Other devices, systems, and methods are also disclosed.
    Type: Grant
    Filed: December 23, 1994
    Date of Patent: July 16, 1996
    Assignee: Texas Instruments Incorporated
    Inventors: Glen R. Haas, Jr., Thomas E. Nagle
  • Patent number: 5392185
    Abstract: In one form of the invention, an Electrostatic Discharge protection device containing at least one heterojunction transistor is disclosed. In another embodiment, an Electrostatic Discharge protection circuit comprises: a first terminal contact 20; an NPN heterojunction bipolar transistor Q2; a PNP bipolar transistor Q1; a base-emitter shunt resistor R2; an emitter of said PNP transistor connected to said first terminal contact; a base of said PNP transistor connected to collector of said NPN transistor; a collector of said PNP transistor connected to a base of said NPN transistor; and an emitter of said NPN transistor connected to a second terminal contact 22, with said base-emitter shunt resistor connected between said base of said NPN transistor and an emitter of said NPN transistor, whereby a low-capacitance device capable of protecting semiconductor devices from electrostatic discharges in excess of 4000 Volts results. Other devices, systems, and methods are also disclosed.
    Type: Grant
    Filed: May 29, 1992
    Date of Patent: February 21, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Glen R. Haas, Jr., Thomas E. Nagle