Abstract: A system for testing a DRAM includes DRAM blocks, the system further includes a processor based built-in self test system for generating a test data pattern, for each DRAM block, performing a write of the test data pattern into the DRAM block, performing a pause for a predetermined period of time, and performing a read of a resulting data pattern from the DRAM block. For each DRAM block, the performing the write of the test pattern into the DRAM block is performed before the performing the pause for the predetermined period of time, and the performing the read of the resulting data pattern from the DRAM block is performed after the performing the pause for the predetermined period of time, and at least a portion of the pause for the predetermined period of time of two or more the DRAM blocks overlap in time.

Abstract: Technique to perform logic and embedded memory tests using logic scan chain testing procedures in parallel with memory built in self test (BIST). This is accomplished with a combination of voltage isolation between memory and logic segments, and isolation between logic and memory test clocks. A test algorithm is introduced to enable and disable the scan chain operation during BIST operation.

Abstract: A method and system for testing an embedded DRAM that includes DRAM blocks. The method including: generating a test data pattern in a processor based BIST system, for each DRAM block, performing a write of the test data pattern into the DRAM block, performing a pause for a predetermined period of time, and performing a read of a resulting data pattern from the DRAM block; where for each DRAM block, the write of the test data pattern into the DRAM block is performed before the pause, and the read of the resulting data pattern from each DRAM block is performed after the pause; where at least a portion of the pause of two or more of the DRAM blocks overlap in time; and for each DRAM block comparing the test data pattern to the resulting data pattern.

Abstract: A method and system for testing a DRAM comprised of DRAM blocks. The method comprises: in a processor based built-in self test system, generating a test data pattern; for each DRAM block, performing a write of the test data pattern into the DRAM block, performing a pause for a predetermined period of time, and performing a read of a resulting data pattern from the DRAM block; wherein for each DRAM block, the performing the write of the test pattern into the DRAM block is performed before the performing the pause for the predetermined period of time, and the performing the read of the resulting data pattern from the DRAM block is performed after the performing the pause for the predetermined period of time; and wherein at least a portion of the pause for the predetermined period of time of two or more the DRAM blocks overlap in time.

Abstract: Technique to perform logic and embedded memory tests using logic scan chain testing procedures in parallel with memory built in self test (BIST). This is accomplished with a combination of voltage isolation between memory and logic segments, and isolation between logic and memory test clocks. A test algorithm is introduced to enable and disable the scan chain operation during BIST operation.

Abstract: A programmable data generator for generating input test data to be applied to a semiconductor memory array is disclosed. In an exemplary embodiment of the invention, the data generator includes a programmable address scramble register which has a plurality of storage locations associated therewith. The plurality of storage locations corresponds to array address bits associated with an address generator. A first exclusive OR (XOR) logic structure is coupled to the address generator and the address scramble register, wherein the first XOR logic structure generates an address-dependent, data scramble output signal that ultimately determines a data pattern to be applied to the memory array.

Abstract: A method for generating a selected subset of memory addresses associated with a semiconductor memory array is disclosed. In an exemplary embodiment of the invention, the method includes configuring an address counter to generate addresses corresponding to locations within the memory array. A mask register is programmed with a series of masking bits, the value of the masking bits determining whether corresponding address bits in the address counter are masked or not masked. Any of the address bits in the address counter corresponding to a masked bit are masked from a counting operation performed by the address counter, thereby causing the address counter to generate the selected subset of memory addresses.