Abstract: Timing for a critical path of a circuit design is optimized by splitting up the path so the synthesis effort to solve the path is appropriately apportioned. Selected nodes of the path are made visible, and internal timing constraints are applied to gates at the visible nodes. The internal timing constraints are translated into physical locations, and placement constraints are applied to the gates based on the physical locations, followed by timing-driven placement. The internal timing constraints can be required arrival times computed using a linear delay model. The placement constraints can include an attractive force between a given one of the selected gates and a corresponding one of the physical locations. The results are better stability control from run to run, and significant savings in power consumption due to less buffering and better gate sizing, with an optimum partition of the path for better routing.

Abstract: Timing for a critical path of a circuit design is optimized by splitting up the path so the synthesis effort to solve the path is appropriately apportioned. Selected nodes of the path are made visible, and internal timing constraints are applied to gates at the visible nodes. The internal timing constraints are translated into physical locations, and placement constraints are applied to the gates based on the physical locations, followed by timing-driven placement. The internal timing constraints can be required arrival times computed using a linear delay model. The placement constraints can include an attractive force between a given one of the selected gates and a corresponding one of the physical locations. The results are better stability control from run to run, and significant savings in power consumption due to less buffering and better gate sizing, with an optimum partition of the path for better routing.

Abstract: Aspects of the invention provide for improving a success rate of an engineering design change (ECO) for an integrated circuit. In one embodiment, aspects of the invention include a method for improving a success rate of an engineering design change (ECO) for an integrated circuit, including: identifying a plurality of spare latches within the integrated circuit; determining an input driver for each of the spare latches; and replacing each input driver with a programmable gate array, such that the programmable gate array is programmed to a functionality of the input driver.

Abstract: Aspects of the invention provide for spare latch distribution for an integrated circuit design. In one embodiment, aspects of the invention include a method of generating a computer system for spare latch distribution in an integration circuit design, the method including: providing a computer system operable to: receive design data for the integrated circuit design, the design data including a plurality of latches; segment the integrated circuit design into a plurality of equal sections; determine a latch density within each of the equal sections; and determine a number of spare latches, based on the latch density, for each of the equal sections. Further, it is understood that the above are performed for each clock domain within the integrated circuit design.

Abstract: A method comprises generating a first behavioral model of a circuit describing a physical circuit in a first configuration. The first configuration comprises a first master latch, a first fanout path, and a logic cone. The first master latch couples to the first fanout path and is configured to receive a first data input signal. The first fanout path comprises a plurality of output sinks, each coupled to the logic cone. The first behavioral model is modified to generate a second behavioral model describing the physical circuit in a second configuration. The second configuration comprises an error circuit and an abstract latch clone based on the first master latch. A configuration file is generated based on the second behavioral model. The configuration file comprises information representing a plurality of instantiated latch clones based on the abstract latch clone, each configured to couple to the first data input signal and to one or more output sinks of the plurality of output sinks.

Abstract: Aspects of the invention provide for spare latch distribution for an integrated circuit design. In one embodiment, aspects of the invention include a method of generating a computer system for spare latch distribution in an integration circuit design, the method including: providing a computer system operable to: receive design data for the integrated circuit design, the design data including a plurality of latches; segment the integrated circuit design into a plurality of equal sections; determine a latch density within each of the equal sections; and determine a number of spare latches, based on the latch density, for each of the equal sections. Further, it is understood that the above are performed for each clock domain within the integrated circuit design.

Abstract: Aspects of the invention provide for improving a success rate of an engineering design change (ECO) for an integrated circuit. In one embodiment, aspects of the invention include a method for improving a success rate of an engineering design change (ECO) for an integrated circuit, including: identifying a plurality of spare latches within the integrated circuit; determining an input driver for each of the spare latches; and replacing each input driver with a programmable gate array, such that the programmable gate array is programmed to a functionality of the input driver.

Abstract: A method includes generating a first behavioral model of a circuit, the first behavioral model describing a physical circuit in a first configuration. The first configuration comprises a first logic structure configured to generate a first intermediate signal based on a received first plurality of inputs. The first configuration further comprises a logic cone configured to generate a scan output based on the first intermediate signal and a plurality of scan inputs. The first behavioral model is modified to generate a second behavioral model describing the physical circuit in a second configuration. The second configuration comprises an error circuit configured to receive the scan output and the first intermediate signal. A testability model is generated based on the second behavioral model, the testability model comprising a first structural representation of the first logic structure.

Abstract: A technique for implementing an engineering change order includes determining spares that are available to implement a modification to a circuit design. One of the available spares is then selected to implement the modification to the circuit design based on performance criteria associated with each of the available spares.

Abstract: A method includes generating a first behavioral model of a circuit, the first behavioral model describing a physical circuit in a first configuration. The first configuration comprises a first logic structure configured to generate a first intermediate signal based on a received first plurality of inputs. The first configuration further comprises a logic cone configured to generate a scan output based on the first intermediate signal and a plurality of scan inputs. The first behavioral model is modified to generate a second behavioral model describing the physical circuit in a second configuration. The second configuration comprises an error circuit configured to receive the scan output and the first intermediate signal. A testability model is generated based on the second behavioral model, the testability model comprising a first structural representation of the first logic structure.

Abstract: A method comprises generating a first behavioral model of a circuit describing a physical circuit in a first configuration. The first configuration comprises a first master latch, a first fanout path, and a logic cone. The first master latch couples to the first fanout path and is configured to receive a first data input signal. The first fanout path comprises a plurality of output sinks, each coupled to the logic cone. The first behavioral model is modified to generate a second behavioral model describing the physical circuit in a second configuration. The second configuration comprises an error circuit and an abstract latch clone based on the first master latch. A configuration file is generated based on the second behavioral model. The configuration file comprises information representing a plurality of instantiated latch clones based on the abstract latch clone, each configured to couple to the first data input signal and to one or more output sinks of the plurality of output sinks.

Abstract: A method, system, and computer program product are provided for achieving timing closure in a clocked logic circuit. For each local clock buffer in a set of local clock buffers, a logic synthesis tool determines a clock control signal input from a set of clock control signal inputs that will drive a clock control signal to the local clock buffer at a target frequency such that a first timing constraint may be met. The operation performed by the logic synthesis tool forms a determined clock control signal input. Responsive to the logic synthesis tool determining the determined clock control signal input, the logic synthesis tool couples the local clock buffer to the determined clock control signal input that drives the clock control signal to the local clock buffer at the target frequency to achieve timing closure in the clocked logic circuit.

Abstract: Disclosed are a method, a system and a computer program product for determining and reporting minterms to aid in implementing an engineering change order (ECO). A Minterm Tracing and Reporting (MTR) utility, which executes on a computer system, receives two or more timing points of an optimized netlist, where one or more of the two or more timing points are received from one or more of a user, a memory medium, and/or a network. For example, a timing point is a primary input, a primary output, or a latch point. After receiving the two or more timing points of the optimized netlist, the MTR utility determines two or more minterms of the optimized netlist. In determining the minterms, from one timing point to a next timing point: a polarity at the timing point may be determined, and a forward trace from the timing point to the next timing point is performed to determine the two or more minterms of the optimized netlist.

Abstract: Disclosed are a method, a system and a computer program product for determining and reporting minterms to aid in implementing an engineering change order (ECO). A Minterm Tracing and Reporting (MTR) utility, which executes on a computer system, receives two or more timing points of an optimized netlist, where one or more of the two or more timing points are received from one or more of a user, a memory medium, and/or a network. For example, a timing point is a primary input, a primary output, or a latch point. After receiving the two or more timing points of the optimized netlist, the MTR utility determines two or more minterms of the optimized netlist. In determining the minterms, from one timing point to a next timing point: a polarity at the timing point may be determined, and a forward trace from the timing point to the next timing point is performed to determine the two or more minterms of the optimized netlist.

Abstract: A technique for implementing an engineering change order (ECO) includes comparing a first hardware description language (HDL) design with a second HDL design. In this case, the second HDL design corresponds to the first HDL design with at least one implemented ECO. The technique identifies differences in latch points, primary inputs, and primary outputs between the first and second HDL designs. The second HDL design is converted to a non-optimized netlist. Logical cones (cones of logic) that feed the latch points, the primary inputs, and the primary outputs are extracted from the non-optimized netlist. Based on the extracted logical cones and the non-optimized netlist, a physical implementation of the second HDL design is synthesized.

Abstract: A technique for implementing an engineering change order includes determining spares that are available to implement a modification to a circuit design. One of the available spares is then selected to implement the modification to the circuit design based on performance criteria associated with each of the available spares.

Abstract: A method, system, and computer program product are provided for achieving timing closure in a clocked logic circuit. For each local clock buffer in a set of local clock buffers, a logic synthesis tool determines a clock control signal input from a set of clock control signal inputs that will drive a clock control signal to the local clock buffer at a target frequency such that a first timing constraint may be met. The operation performed by the logic synthesis tool forms a determined clock control signal input. Responsive to the logic synthesis tool determining the determined clock control signal input, the logic synthesis tool couples the local clock buffer to the determined clock control signal input that drives the clock control signal to the local clock buffer at the target frequency to achieve timing closure in the clocked logic circuit.

Abstract: A method is provided to remove redundancies in multi-level logic networks caused by reconverging signals at Boolean sum and product nodes. Generally, sum and product nodes which have potential redundancies are first identified. For each reconvergent signal at each of the nodes, it is determined whether it introduces redundancies using nondestructive Boolean analysis. No two-level expansion is made of the logic network. Moreover, for each confirmed redundancy, a redundant term is identified using Boolean analysis. Finally, the redundancy is removed, if desirable.