Abstract: A method includes providing at least one wafer having a process layer formed thereon. A surface of the process layer is polished using a first polishing process that is comprised of a slurry and a first polishing pad. The slurry is removed from the surface of the process layer. The surface of the process layer is planarized using a substantially slurryless second polishing process that is comprised of a second polishing pad that is more abrasive than the first polishing pad. A system includes a polishing tool and a process controller. The polishing tool is adapted to receive at least one wafer having a process layer formed thereon. The polishing tool is a adapted to polish a surface of the process layer using a first polishing process that is comprised of a slurry and a first polishing pad and remove the slurry from the surface of the process layer.

Abstract: A method is provided to enhance endpoint detection during via etching in the processing of a semiconductor wafer. The method includes forming a first process layer and a second process layer above the first process layer. A first masking layer is formed above at least a portion of the second process layer, leaving an outer edge portion of at least the second process layer exposed. Thereafter, an etching process is used to remove the outer edge portion of the first and second layers. Once the etching is complete, the first masking layer is removed, and a second masking layer is formed above the second process layer. The second masking layer is patterned to expose portions of the first process layer, and then an etching process substantially removes the exposed portions of the first process layer to form the vias.

Abstract: A method for forming a semiconductor device includes providing a substrate and forming a gate stack on the substrate. The gate stack includes a gate electrode having a thickness. Source/drain regions are formed in the substrate proximate the gate stack, and a first metal silicide layer is formed over the source drain regions. The thickness of the gate electrode is reduced, and a second metal silicide layer is formed over the reduced thickness gate electrode.

Abstract: A method of forming a transistor includes forming a source/drain implant in the initial processing stages just after the formation of the isolation and active regions on the substrate. A uniform nitride layer is formed over the surface of the substrate on top of a dielectric layer. A silicide metal is then deposited and reacted with the underlying silicon to form a salicide over the source and drain regions. A second dielectric layer is then formed on top of the salicide and is formed to be selective relative to the nitride layer. Thereafter, the nitride layer is removed and a final gate dielectric is then formed. Finally, a metal gate conductor is formed on top of the gate dielectric. The metal gate conductor is formed only after all annealing steps are performed to prevent the metal from spiking through the gate dielectric thereby ruining the device.

Abstract: A method of forming a semiconductor device includes forming a first gate electrode over a substrate and then forming a spacer on at least one sidewall of the first gate electrode. A second gate electrode is formed over the substrate after forming the spacer. A first dopant is implanted into the substrate to form a first heavily doped active region adjacent to the spacer and spaced from the first gate electrode and a second heavily doped active region adjacent to the second gate electrode. The spacer is then removed and a second dopant is implanted into the substrate to form a lightly doped active region adjacent to the first gate electrode. In some instances, gate dielectrics for the first and second gate electrodes are formed using different materials and/or having different thicknesses.

Abstract: A method for reducing die loss in a semiconductor fabrication process which employs titanium nitride and HDP oxide is provided. In the fabrication of multilevel interconnect structures, there is a propensity for defect formation in a process in which titanium nitride and HDP oxide layers are in contact along the edge of a semiconductor substrate. A dielectric interlayer is provided which improves the interfacial properties between titanium nitride and HDP oxide and thereby reduces defects caused by delamination at the titanium nitride/HDP oxide interface.

Abstract: A method for fabricating an integrated circuit is presented wherein a trench is patterned in a field region of a semiconductor substrate. The trench is defined within the semiconductor substrate by a trench floor and trench sidewalls. A trench surface boundary is defined where the trench sidewalls intersect the upper surface of the semiconductor substrate. The trench may be filled with a trench fill material. A protective layer is then formed above the trench. The protective layer covers the trench and laterally extends above the semiconductor substrate at least a first distance beyond the trench surface boundaries.

Abstract: An integrated circuit fabrication process is provided for forming a transistor having an ultra short channel length dictated by the width of a sidewall spacer which either embodies a gate conductor for the transistor or is used to pattern an underlying gate conductor. In one embodiment, the sidewall spacers are formed upon and extending laterally from the opposed sidewall surfaces of a sacrificial material. The sidewall surfaces of the sacrificial material are defined by forming the sacrificial material within an opening interposed laterally between vertically extending sidewalls which bound a gate dielectric. An upper portion of the gate dielectric is removed to partially expose the sidewall surfaces arranged at the periphery of the sacrificial material. Polysilicon spacers are formed exclusively upon the sidewall surfaces of the sacrificial material to define a pair of gate conductors having relatively small lateral widths.

Abstract: A method for forming an isolation trench in a semiconductor substrate that is substantially free of voids. The method includes forming a dielectric masking layer above a semiconductor substrate. An opening is preferably formed through the masking layer and partially into the semiconductor substrate forming a shallow trench within the semiconductor substrate. Optionally, thermal oxidation of the trench may be performed to form an oxide layer within the trench. A spacer layer is preferably deposited across the exposed surface of the topography. The spacer layer is preferably etched to form spacers directly adjacent to opposed sidewall surfaces of the trench. The isolation trench may then be filled with an isolation dielectric. The presence of the spacers within the isolation trench preferably causes the lower portions of the trench to fill up faster than the upper portions. In this manner the trench may be filled without the formation of voids.

Abstract: A high performance semiconductor device structure and method of making the same include a bulk semiconductor substrate and an upper level silicon substrate. The upper level silicon substrate includes a low-K dielectric layer and a silicon substrate layer. The low-K dielectric layer is formed on the bulk semiconductor substrate, the low-K dielectric layer having a dielectric K-value in the range of 2.0-3.8. The silicon substrate layer and low-K dielectric layer are then patterned into the upper level substrate in a first region and the bulk semiconductor substrate is exposed in a second region. A gate oxide layer is formed over the upper level substrate in the first region and over the exposed bulk semiconductor substrate in the second region. Lastly, transistor device formations are formed in the upper level substrate and in the bulk semiconductor substrate.

Abstract: A method and structure are provided for an IGFET which has elevated source/drain regions and polished gate electrode. The IGFET provides raised doped polysilicon regions between the source/drain areas and subsequent metallization layers. The doped polysilicon regions are scalable. Integration of elevated source/drain regions provides a shallow junction for high performance IGFET design. A refractory metal gate is provided without sacrificing the fabrication advantage of self-aligned techniques. A method to produce an IGFET which incorporates both of the above advantages into a single device, with relatively few process steps, is also provided. Fabricating the gate electrode in this manner will enable metal gate electrodes to be integrated with source/drain structure.

Abstract: A method for the manufacture of a semiconductor device with trench isolation regions includes forming at least one trench in a substrate to define one or more isolation regions. At least a portion of the trench is filled with a flowable oxide-generating material which is then formed into an oxide layer. An optional dielectric layer can be deposited over the oxide layer. A portion of the oxide layer and/or the optional dielectric layer is removed to generate a substantially planer surface.

Abstract: The present invention is directed to a new and improved technique for formation of metal oxide semiconductor field effect transistors. In particular, the method involves formation of an initial gate structure that is wider than the desired final channel length of the completed transistor. Thereafter, an initial heavy-doping step is applied to the drain and source regions of the device. The width of the gate structure is then patterned and etched back to the desired final channel length of the device. A second, light-doping LDD implant is performed to complete the source and drain regions of the finished device.

Abstract: A transistor and a method of making the same are provided. The method includes the step of forming a gate dielectric layer on the substrate where the gate dielectric layer is composed of an aluminum oxide containing material. A gate electrode is formed on the gate dielectric layer and first and second source/drain regions are formed in the substrate laterally separated to define a channel region beneath the gate electrode. The aluminum oxide containing material may be, for example, Al.sub.2 O.sub.3. Aluminum oxide provides for a gate dielectric with a thin equivalent thickness of oxide in a potentially single crystal form.

Abstract: A method for isolating semiconductor devices comprising providing a semiconductor substrate. The semiconductor substrate includes a first pair of source/drain regions on either side of a first channel region and a second pair of source/drain regions on either side of a second channel region. One of the first pair of source/drain regions is proximal to one of the second pair of source/drain regions. First and second laterally displaced MOS transistors are formed partially within the semiconductor substrate. An isolation trench is formed through the proximal source/drain regions and the trench is filled with a trench dielectric material such that the proximal source/drain regions are electrically isolated whereby the first transistor is electrically isolated from the second transistor.

Abstract: A semiconductor device having gate electrodes with different gate insulators and a process for fabricating such device is provided. Consistent with one embodiment of the invention, a semiconductor device is provided in which a first gate insulator is formed over a first region of a substrate. A second gate insulator, different than the first gate insulator, is formed over a second region of the substrate. Finally, one or more gate electrodes are formed over each of the first and second gate insulators. The first gate insulator may, for example, have a permittivity and/or a thickness which is different from that of the second gate insulator. For example, the first gate insulator may have a permittivity greater than 20, and the second gate insulator may have a permittivity less than 10.

Abstract: A memory device having a high performance stacked dielectric sandwiched between two polysilicon plates and method of fabrication thereof is provided. A memory device, in accordance with an embodiment, includes two polysilicon plates and a high permittivity dielectric stack disposed between the two polysilicon plates. The high permittivity dielectric stack includes a relatively high permittivity layer and two relatively low permittivity buffer layers. Each buffer layer is disposed between the relatively high permittivity layer and a respective one of the two polysilicon plates. The high permittivity layer may, for example, be a barium strontium titanate and the buffer layers may each include a layer of silicon nitride adjacent the respective polysilicon plate and a layer of titanium dioxide between the silicon nitride and the barium strontium titanate. The new high performance dielectric layer can, for example, increase the speed and reliability of the memory device as compared to conventional memory devices.

Abstract: A method of forming a semiconductor device by using a pillar to form a contact with an active region of the device. A semiconductor device is formed by forming one or more active regions on a substrate of the semiconductor device and forming a pillar over at least a portion of one of the active regions. An insulating film selective to the pillar is provided over portions of the substrate adjacent the pillar. The pillar is then used to form a conductive contact with the active region over which it is formed. In one embodiment, the pillar is formed from a photoresist, while in other embodiments, the pillar is formed from a conductor material such as a metal. The active region may form a source/drain region or a gate electrode.

Abstract: An integrated circuit fabrication process is provided in which a sub-level local interconnect is formed between a gate conductor of one transistor and a junction of another transistor. The formation of a sub-level local interconnect allows for higher packing density by removing the local interconnect to a sub-level dielectrically spaced from possibly other local interconnects and from the distal interconnect normally associated with device interconnection. A semiconductor topography is provided which includes a first transistor laterally spaced from a second transistor, the transistors being arranged upon and within the substrate. An interlevel dielectric is deposited across the semiconductor topography. A portion of the interlevel dielectric is removed to form a trench. The trench is then filled with a conductive material to form a local interconnect extending horizontally above a portion of the first transistor and a portion of the second transistor.

Abstract: A semiconductor device having a nitrogen enhanced high permittivity gate insulating layer and a process for manufacturing such a device is provided. Consistent with one embodiment, a high permittivity gate insulating layer is formed over a substrate using a nitrogen bearing gas. The gate insulating layer has a dielectric constant of at least 20. At least one gate electrode is formed over the high permittivity gate insulating layer. An optional nitride capping layer can be formed between the high permittivity gate insulating layer and the gate electrode. The nitrogen bearing gas may include one or more nitrogen bearing species, such as NO, NF.sub.3 or N2, for example. The use of nitrogen in the formation of a high permittivity gate insulating layer can, for example, reduce oxidation of the high permittivity layer and increase the ability to control the characteristics of the gate insulating layer.