Patents by Inventor Thomas E. Tkacik

Thomas E. Tkacik has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10127998
    Abstract: A method of programming a memory includes selecting a logic state for programming a first bitcell of the memory. A first one-time-programmable (OTP) element of the first bitcell is programmed using a first set of conditions intended to achieve a first target resistance in accordance with the selected logic state which results in a first degree of programming of the first OTP element. A second OTP element of the first bitcell is programmed using a second set of conditions different from the first set of conditions intended to achieve a second target resistance in accordance with the selected logic state which results in a second degree of programming of the second OTP element, wherein the first and second degrees of programming are visually indistinguishable.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: November 13, 2018
    Assignee: NXP USA, Inc.
    Inventors: Alexander B. Hoefler, Thomas E. Tkacik
  • Patent number: 9954681
    Abstract: A method of encrypting data on a memory device includes receiving a memory transaction request at an inline encryption engine coupled between a processing core and switch fabric in a system on a chip (SOC). The memory transaction request includes a context component and a data component. The context component is analyzed to determine whether the data component will be stored in an encrypted memory region. If the data component will be stored in an encrypted memory region, the data component is encrypted and communicated to a location in the encrypted memory region. The location is based at least on the context component.
    Type: Grant
    Filed: June 10, 2015
    Date of Patent: April 24, 2018
    Assignee: NXP USA, Inc.
    Inventors: Lawrence L. Case, Charles E. Cannon, Mingle Sun, Thomas E. Tkacik
  • Publication number: 20160364343
    Abstract: A method of encrypting data on a memory device includes receiving a memory transaction request at an inline encryption engine coupled between a processing core and switch fabric in a system on a chip (SOC). The memory transaction request includes a context component and a data component. The context component is analyzed to determine whether the data component will be stored in an encrypted memory region. If the data component will be stored in an encrypted memory region, the data component is encrypted and communicated to a location in the encrypted memory region. The location is based at least on the context component.
    Type: Application
    Filed: June 10, 2015
    Publication date: December 15, 2016
    Inventors: LAWRENCE L. CASE, Charles E. Cannon, Mingle Sun, Thomas E. Tkacik
  • Patent number: 9436248
    Abstract: A semiconductor device includes a processing system including a section of power domain circuitry and a section of coin cell power domain circuitry. The coin cell power domain circuitry is configured to, when power is initially provided to the coin cell power domain circuitry, using power provided by a power management circuit as feedback to determine that the power management circuit provides the power in response to a power request signal being a toggle signal, and determine that the power management circuit provides the power in response to the power request signal being a pulse signal.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: September 6, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Lawrence L. Case, Matthew W. Brocker, Mingle Sun, Thomas E. Tkacik
  • Patent number: 9430658
    Abstract: To securely configure an electronic circuit and provision a product that includes the electronic circuit, a first entity (e.g., a chip manufacturer) embeds one or more secret values into copies of the circuit. A second entity (e.g., an OEM): 1) derives a trust anchor from a code signing public key; 2) embeds the trust anchor in a first circuit copy; 3) causes the first circuit copy to generate a secret key derived from the trust anchor and the embedded secret value(s); 4) signs provisioning code using a code signing private key; and 5) sends the code signing public key, the trust anchor, and the signed provisioning code to a third entity (e.g., a product manufacturer). The third entity embeds the trust anchor in a second circuit copy and causes it to: 1) generate the secret key; 2) verify the signature of the signed provisioning code using the code signing public key; and 3) launch the provisioning code.
    Type: Grant
    Filed: December 16, 2014
    Date of Patent: August 30, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Carlin R. Covey, Lawrence L. Case, Thomas E. Tkacik
  • Patent number: 9424200
    Abstract: A run-time integrity checking (RTIC) method compatible with memory having at least portions that store data that is changed over time or at least portions configured as virtual memory is provided. For example, the method may comprise storing a table of page entries and accessing the table of page entries by, as an example, an operating system or, as another example, a hypervisor to perform RTIC on memory in which, as an example, an operating system, as another example, a hypervisor, or, as yet another example, application software is stored. The table may, for example, be stored in secure memory or in external memory. The page entry comprises a hash value for the page and a hash valid indicator indicating the validity status of the hash value. The page entry may further comprise a residency indicator indicating a residency status of the memory page.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: August 23, 2016
    Assignee: FREESCALE SEMICONDUCTOR, INC.
    Inventors: Thomas E. Tkacik, Matthew W. Brocker, Carlin R. Covey
  • Patent number: 9384153
    Abstract: Embodiments of electronic circuits, computer systems, and associated methods include a module that accesses memory using virtual addressing, the memory including local memory that is local to the module and nonlocal memory that is accessible via a system bus coupled to the module, the module including logic coupled to the local memory via a local bus. The logic is configured to receive a memory access specified to a virtual address, determine whether the virtual address is within the local memory, and direct the memory access either to the local memory via the local bus or to the nonlocal memory via the system bus based on the determination.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: July 5, 2016
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Thomas E. Tkacik, Charles E. Cannon, Carlin R. Covey, David H. Hartley, Rodney D. Ziolowski
  • Publication number: 20160171223
    Abstract: To securely configure an electronic circuit and provision a product that includes the electronic circuit, a first entity (e.g., a chip manufacturer) embeds one or more secret values into copies of the circuit. A second entity (e.g., an OEM): 1) derives a trust anchor from a code signing public key; 2) embeds the trust anchor in a first circuit copy; 3) causes the first circuit copy to generate a secret key derived from the trust anchor and the embedded secret value(s); 4) signs provisioning code using a code signing private key; and 5) sends the code signing public key, the trust anchor, and the signed provisioning code to a third entity (e.g., a product manufacturer). The third entity embeds the trust anchor in a second circuit copy and causes it to: 1) generate the secret key; 2) verify the signature of the signed provisioning code using the code signing public key; and 3) launch the provisioning code.
    Type: Application
    Filed: December 16, 2014
    Publication date: June 16, 2016
    Inventors: CARLIN R. COVEY, LAWRENCE L. CASE, THOMAS E. TKACIK
  • Patent number: 9158499
    Abstract: Embodiments of an electronic circuit comprise a module, such as a security module, configured to perform cryptographic processing for a predetermined security protocol that includes random number checking. The security module is controlled by a descriptor that includes instructions that cause the security module to access a generated random number, compare the generated random number to a random number stored during a previous execution of the descriptor, and generate an error signal when the generated random number and the previous execution random number are equal.
    Type: Grant
    Filed: April 30, 2012
    Date of Patent: October 13, 2015
    Assignee: FREESCALE SEMICONDUCTOR, INC
    Inventors: Michael J. Torla, Steven D. Millman, Thomas E. Tkacik, Frank James
  • Patent number: 9135129
    Abstract: A method and apparatus for testing operation of a random number generator (RNG) testing circuit are provided. In accordance with at least one embodiment, a first RNG output value obtained from a RNG is stored in a first register. In response to activation of a test mode to simulate a faulty RNG, the first RNG output value is stored in a second register. The first RNG output value in the first register is compared to the first RNG output value in the second register. In response to the comparing, a RNG failure signal is provided at a RNG testing circuit output of the RNG testing circuit. In accordance with at least one embodiment, sequential and combinational logic can simulate a faulty RNG. Accordingly, simulation of a faulty RNG may be performed to test a RNG testing circuit even when the RNG is not faulty.
    Type: Grant
    Filed: January 11, 2013
    Date of Patent: September 15, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Matthew W. Brocker, Steven E. Cornelius, Thomas E. Tkacik
  • Patent number: 9129536
    Abstract: Embodiments of electronic circuits enable security of sensitive data in a design and manufacturing process that includes multiple parties. An embodiment of an electronic circuit can include a private key embedded within the electronic circuit that is derived from a plurality of components including at least one component known only to the electronic circuit and at least one immutable value cryptographically bound into messages and residing on the electronic circuit, public key generation logic that generates a public key to match the private key, and message signing logic that signs messages with the private key.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: September 8, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Thomas E. Tkacik, Lawrence L. Case, Carlin R. Covey, David H. Hartley, Rodney D. Ziolkowski
  • Patent number: 9100189
    Abstract: Embodiments include methods for securely provisioning copies of an electronic circuit. A first entity embeds one or more secret values into copies of the circuit. A second entity: 1) embeds a trust anchor in a first copy of the circuit; 2) causes the circuit to generate a message signing key pair using the trust anchor and the embedded secret value(s); 3) signs provisioning code using a code signing private key; and 4) sends a corresponding code signing public key, the trust anchor, and the signed provisioning code to a third entity. The third entity embeds the trust anchor in a second copy of the circuit and causes the circuit to: 1) generate the message signing private key; 2) verify the signature of the signed provisioning code using the code signing public key; and 3) launch the provisioning code on the circuit.
    Type: Grant
    Filed: August 21, 2013
    Date of Patent: August 4, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: David H. Hartley, Thomas E. Tkacik, Carlin R. Covey, Lawrence L. Case, Rodney D. Ziolkowski
  • Patent number: 9100174
    Abstract: Embodiments include methods for securely provisioning copies of an electronic circuit. A first entity (e.g., a chip manufacturer) embeds one or more secret values into copies of the electronic circuit. A second entity (e.g., an OEM): 1) embeds a trust anchor in a first copy of the electronic circuit; 2) causes the electronic circuit to generate a message signing key pair using the trust anchor and the embedded secret value(s); 3) signs provisioning code using a code signing private key; and 4) sends a corresponding code signing public key, the trust anchor, and the signed provisioning code to a third entity (e.g., a product manufacturer). The third entity embeds the trust anchor in a second copy of the electronic circuit and causes the electronic circuit to: 1) generate the message signing private key; 2) verify the signature of the signed provisioning code using the code signing public key; and 3) launch the provisioning code on the electronic circuit.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: August 4, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: David H. Hartley, Thomas E. Tkacik, Carlin R. Covey, Lawrence L. Case, Rodney D. Ziolkowski
  • Patent number: 9092283
    Abstract: Methods and systems for producing random numbers include a random number generator with a first port and a second port. The first port is configured to receive a first type of random data request, and the random number generator is configured to generate first random data while the first type of request is asserted on the first port. The second port is configured to receive a second type of random data request, and the random number generator is configured to generate only a specified length of second random data in response to receiving the second type of request on the second port. An embodiment of a system also includes a data structure configured to store multiple random values, which are derived from the first random data generated by the random number generator in response to the first type of random data request.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: July 28, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Thomas E. Tkacik, David G. Abdoo, Matthew W. Brocker, Steven D. Millman
  • Patent number: 9094205
    Abstract: Embodiments of methods of provisioning an electronic circuit enable security of sensitive data in a design and manufacturing process that includes multiple parties. In an illustrative embodiment, a method of provisioning an electronic circuit includes generating at least one secret value, embedding the at least one secret value into the electronic circuit, programming into the electronic circuit a private key derivation function that derives the private key from the at least one secret value and a trust anchor, and programming into the electronic circuit a public key generation function that generates a public key matching the private key. The method can further include receiving for execution trust anchor-authenticated logic that contacts a predetermined actor of the plurality of distinct actors and communicates to the predetermined actor a message signed with the private key.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: July 28, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: David H. Hartley, Thomas E. Tkacik, Carlin R. Covey, Lawrence L. Case, Rodney D. Ziolkowski
  • Patent number: 9075674
    Abstract: Embodiments include bitstring generators and methods of their operation. A sampling parameter of the bitstring generator is set to a current value, and values of one or more bits are then repeatedly sampled based on the current value of the sampling parameter. The repeated sampling results in a set of test bits, which is analyzed to determine a randomness measurement associated with the set of test bits. A determination is made whether the randomness measurement meets a criterion. If not, the current value of the sampling parameter is changed to a different value that corresponds to a lower probability of being able to correctly predict the values of the one or more bits produced by the bitstring generator. The steps of repeatedly sampling, analyzing the set of test bits, and determining whether the randomness measurement meets the criteria are then repeated.
    Type: Grant
    Filed: December 12, 2012
    Date of Patent: July 7, 2015
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Thomas E. Tkacik, David G. Abdoo
  • Publication number: 20150085557
    Abstract: A method of programming a memory includes selecting a logic state for programming a first bitcell of the memory. A first one-time-programmable (OTP) element of the first bitcell is programmed using a first set of conditions intended to achieve a first target resistance in accordance with the selected logic state which results in a first degree of programming of the first OTP element. A second OTP element of the first bitcell is programmed using a second set of conditions different from the first set of conditions intended to achieve a second target resistance in accordance with the selected logic state which results in a second degree of programming of the second OTP element, wherein the first and second degrees of programming are visually indistinguishable.
    Type: Application
    Filed: September 26, 2013
    Publication date: March 26, 2015
    Inventors: Alexander B. Hoefler, Thomas E. Tkacik
  • Publication number: 20150039916
    Abstract: A semiconductor device includes a processing system including a section of power domain circuitry and a section of coin cell power domain circuitry. The coin cell power domain circuitry is configured to, when power is initially provided to the coin cell power domain circuitry, using power provided by a power management circuit as feedback to determine that the power management circuit provides the power in response to a power request signal being a toggle signal, and determine that the power management circuit provides the power in response to the power request signal being a pulse signal.
    Type: Application
    Filed: July 31, 2013
    Publication date: February 5, 2015
    Inventors: Lawrence L. Case, Matthew W. Brocker, Mingle Sun, Thomas E. Tkacik
  • Patent number: 8856198
    Abstract: Embodiments of methods and systems for producing random values include a first module that provides a random data request (e.g., a request for an unspecified length of random data) to a random number generator. The random number generator generates random data in response to the random data request, and multiple random values derived from the random data are stored in a buffer. In response to receiving a request for a random value (e.g., an initialization vector), the first module produces the random value based on the multiple random values stored in the buffer. The system also may be configured to receive requests for other types of random values, and to fulfill those requests using random data that is not buffered (e.g., random data that is received directly from the random number generator in response to a request for a specified length of random data).
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: October 7, 2014
    Assignee: Freescale Semiconductor, Inc.
    Inventors: David G. Abdoo, Matthew W. Brocker, Steven D. Millman, Thomas E. Tkacik
  • Publication number: 20140281354
    Abstract: A run-time integrity checking (RTIC) method compatible with memory having at least portions that store data that is changed over time or at least portions configured as virtual memory is provided. For example, the method may comprise storing a table of page entries and accessing the table of page entries by, as an example, an operating system or, as another example, a hypervisor to perform RTIC on memory in which, as an example, an operating system, as another example, a hypervisor, or, as yet another example, application software is stored. The table may, for example, be stored in secure memory or in external memory. The page entry comprises a hash value for the page and a hash valid indicator indicating the validity status of the hash value. The page entry may further comprise a residency indicator indicating a residency status of the memory page.
    Type: Application
    Filed: March 15, 2013
    Publication date: September 18, 2014
    Inventors: Thomas E. Tkacik, Matthew W. Brocker, Carlin R. Covey