Abstract: A bus translator is provided to translate the internal bus structure of a self-contained processor system to a system bus which is easily compatible with a plurality of different external components. In particular, the bus translator translates the packetized multiplexed internal bus to a de-multiplexed bus. The translator further provides the ability to add wait states to the transactions in order to accommodate slower memories and devices coupled to the system bus. Furthermore, the translator accommodates bus burst logic by providing an auto-increment addressing capability. In addition, as the processor operates on 32-bit words and coupled devices may operate on a smaller word size, the bus translator of the present invention provides a byte enable register file for performing byte operations within the 32-bit word operations of the system. Finally, the bus translator also provides accurate parity generation and checking on a byte basis.