Abstract: A combination watchdog timer and input voltage level detector circuit is coupled to a microcomputer (or microprocessor) for insuring proper operation thereof under various conditions. The watchdog timer is coupled to the microcomputer and is responsive to a status signal output by the microcomputer indicating the operating state thereof. Failure of the watchdog circuit to detect the status signal indicates that the microcomputer has become unstable or is in a locked up condition and causes the watchdog circuit to initiate a microcomputer reset by means of a reset trigger circuit. A voltage level detector is coupled to the input voltage source and to the reset trigger circuit for similarly initiating the resetting of the microcomputer in the event the input voltage to the microcomputer drops below a predetermined value.