Abstract: An induction heating system can comprise a furnace chamber comprising a non-magnetic and non-conductive furnace wall; at least one induction heating coil surrounding an outer side of the furnace wall in a length direction (z) of the furnace chamber; and a holding and pressing construction. The holding and pressing construction can be designed to hold an arrangement to be placed within the furnace chamber, and the holding and pressing construction can apply a pressure on a proximal end and a distal end of the arrangement in the length direction of the chamber.

Abstract: A thermoelectric element can comprise a thermoelectric body and a multi-layer contact structure. The multi-layer contact structure can contain a first metal layer overlying a surface of the thermoelectric body and a second metal layer directly overlying the first metal layer, wherein the first metal layer and the second metal layer include the same metal, and the first metal layer has a different phase than the second metal layer.

Abstract: A thermoelectric device can comprise at least one first thermoelectric element, at least one second thermoelectric element, and a bridging structure. The bridging structure can include a bridging layer comprising a silver-gallium alloy. The silver-gallium alloy containing a bridging layer can provide flexibility and stress release to the thermoelectric device when subjected to multiple heating cycles, and may have a very low electrical resistance and thermal resistance.

Abstract: A thermoelectric device can comprise at least one first thermoelectric element, at least one second thermoelectric element, and a bridging structure. The bridging structure can include a bridging layer comprising a silver-gallium alloy. The silver-gallium alloy containing a bridging layer can provide flexibility and stress release to the thermoelectric device when subjected to multiple heating cycles, and may have a very low electrical resistance and thermal resistance.

Abstract: An induction heating system can comprise a furnace chamber comprising a non-magnetic and non-conductive furnace wall; at least one induction heating coil surrounding an outer side of the furnace wall in a length direction (z) of the furnace chamber; and a holding and pressing construction. The holding and pressing construction can be designed to hold an arrangement to be placed within the furnace chamber, and the holding and pressing construction can apply a pressure on a proximal end and a distal end of the arrangement in the length direction of the chamber.

Abstract: A thermoelectric element can comprise a thermoelectric body, a first contact, and a second contact structure, wherein the first and/or second contact structure can comprise at least one porous metal structure embedded within an outer region of the thermoelectric body, and at least one metal layer overlying the outer region of the thermoelectric body and being in direct contact with the embedded porous metal structure. A method of making the thermoelectric element can include embedding the at least one porous metal structure within the outer region of the thermoelectric body by induction heating, followed by electroplating of the at least one metal layer.

Abstract: A thermoelectric element can comprise a thermoelectric body and a multi-layer contact structure. The multi-layer contact structure can contain a first metal layer overlying a surface of the thermoelectric body and a second metal layer directly overlying the first metal layer, wherein the first metal layer and the second metal layer include the same metal, and the first metal layer has a different phase than the second metal layer.

Abstract: A thermoelectric device, module, and system, and method for and method for making is provided. The thermoelectric device (200) having a first and second elements (202 and 204). The first and second elements (202 and 204) having first and second portions (206 and 208), and third and fourth portions (212 and 214) with first and second regions (210 and 216) connected between the first and second portions (206 and 208) and third and fourth portions (112 and 114), respectively. The first and second portions (206 and 208) and third and fourth portions (112 and 114) are electrically coupled though regions (210 and 216) and with thermal conductance between first and second portions (206 and 208) and third and fourth portions (212 and 214) being inhibited by regions (110 and 116), respectively.

Abstract: A thermoelectric device, module, and system, and method for and method for making is provided. The thermoelectric device (200) having a first and second elements (202 and 204). The first and second elements (202 and 204) having first and second portions (206 and 208), and third and fourth portions (212 and 214) with first and second regions (210 and 216) connected between the first and second portions (206 and 208) and third and fourth portions (112 and 114), respectively. The first and second portions (206 and 208) and third and fourth portions (112 and 114) are electrically coupled though regions (210 and 216) and with thermal conductance between first and second portions (206 and 208) and third and fourth portions (212 and 214) being inhibited by regions (110 and 116), respectively.

Abstract: In one example embodiment, an integrated semiconductor circuit (400) is provided. The integrated circuit (400) comprises a substrate (430) comprising a first material and a first electronic device (455) comprising a first depressed region (415) within the substrate (430) and a set of first device contact locations (475) in a contact level (300). The integrated circuit (400) further comprises a second electronic device 450 comprising a set of second device contact locations (451) in the contact level (300) and a second material (420) in the first depressed (415) region having a lattice mismatch with the first material.

Abstract: An exemplary slot antenna having an antenna cavity that extends over multiple layers is provided. The slot antenna includes a reference conductive layer, a radiating conductive layer having at least one slot opening, one or more intermediate conductive layers disposed between the reference conductive layer and the radiating conductive layer, and two or more dielectric layers. The two or more dielectric layers include at least a first dielectric layer disposed between the reference conductive layer and the one or more intermediate conductive layers and a second dielectric layer disposed between the one or more intermediate conductive layers and the radiating conductive layer. Each of the one or more intermediate conductive layers includes at least one opening substantially devoid of conductive material. Due to its reduced footprint in the x-y plane, the multilayer slot antenna may be embedded in an integrated circuit package for use in a wireless device.

Abstract: In one example embodiment, an integrated semiconductor circuit (400) is provided. The integrated circuit (400) comprises a substrate (430) comprising a first material and a first electronic device (455) comprising a first depressed region (415) within the substrate (430) and a set of first device contact locations (475) in a contact level (300). The integrated circuit (400) further comprises a second electronic device 450 comprising a set of second device contact locations (451) in the contact level (300) and a second material (420) in the first depressed (415) region having a lattice mismatch with the first material.

Abstract: A circuit and method protect a transistor (68, 70) from damage when controlling an input signal (V.sub.PROG) that exceeds a gate to channel stress voltage of the transistor. A small, low current protection transistor (64, 66) is serially coupled to the gate electrode of the transistor being protected. The gate of the protection transistor is biased to a voltage (V.sub.P, V.sub.N) of lower magnitude than the input signal to limit the voltage applied to the gate of the protected transistor to a value within the stress voltage of the protected transistor.

Abstract: In a first approach, an interconnect structure (10) reduces peak localized interconnect current density by distributing current flow around the perimeter (22) of an interlevel connector (14) in a semiconductor device. A first interconnect level (12) is connected to a second interconnect level by the interlevel connector (14), and the perimeter (22) of the interlevel connector (14) is located at the juncture between the first interconnect level (12) and the interlevel connector (14). The first interconnect level (12) has two or more fingers (16,18,20) protruding therefrom that connect to the perimeter (22) of the interlevel connector (14). At least one opening (36, 38) is disposed between two of the fingers (16,18,20) for dividing current flow.

Abstract: An insulated gate field effect transistor (IGFET) structure (10) includes a source region (14) and a drain region (16) formed in an impurity well (13). A channel region (18) separates the source region (14) from the drain region (16). In one embodiment, a unilateral extension region (17) is formed adjacent the source region (14) only and extends into the channel region (18). The unilateral extension region (17) has a peak dopant concentration at a depth (23) and a lateral distance (24) to provide punchthrough resistance. The IGFET structure (10) is suitable for low (i.e., 0.2-0.3 volts) to medium (0.5-0.6 volts) threshold voltage reduced channel length applications.

Abstract: In a first approach, an interconnect structure (10) reduces peak localized interconnect current density by distributing current flow around the perimeter (22) of an interlevel connector (14) in a semiconductor device. A first interconnect level (12) is connected to a second interconnect level by the interlevel connector (14), and the perimeter (22) of the interlevel connector (14) is located at the juncture between the first interconnect level (12) and the interlevel connector (14). The first interconnect level (12) has two or more fingers (16,18,20) protruding therefrom that connect to the perimeter (22) of the interlevel connector (14). At least one opening (36,38) is disposed between two of the fingers (16,18,20) for dividing current flow.

Abstract: A method is provided for forming a right angle (30) on a chromeless phase-shift mask (31). A first phase-shift element (32) and a second phase-shift element (33) are positioned at a ninety degree angle, on the chromeless phase-shift mask (31), wherein there is a predetermined space (34) between the first and second phase-shift elements (32,33). The space between the phase-shift elements eliminates hot spot formation that causes unintentional exposure of the semiconductor substrate.