Abstract: Clock recovery from transmitted data signals is carried out entirely digitally, and in a manner that is essentially insensitive to dynamic changes in the phase of the data signal. To this end, at least four phase-shifted sample signals are produced from a predetermined time signal. At least two of these phase-shifted sample signals are selected as a function of the respective phase angles with respect to the data signal, and in each case are supplied separately to a device for time sampling of the data signal with the selected sample signal. One of the devices in each case is connected to an output device for the data signal as a function of the respective phase separations between the data signal and the selected phase-shifted sample signals.

Abstract: Clock recovery from transmitted data signals is carried out entirely digitally, and in a manner that is essentially insensitive to dynamic changes in the phase of the data signal. To this end, at least four phase-shifted sample signals are produced from a predetermined time signal. At least two of these phase-shifted sample signals are selected as a function of the respective phase angles with respect to the data signal, and in each case are supplied separately to a device for time sampling of the data signal with the selected sample signal. One of the devices in each case is connected to an output device for the data signal as a function of the respective phase separations between the data signal and the selected phase-shifted sample signals.

Abstract: The invention relates to a transmission system comprising a phase-locked loop (12) which includes a phase comparator (15) for comparing an oscillator signal with a reference signal and for generating a comparison signal, and an oscillator which is provided for receiving a control signal derived from the comparison signal. The oscillator arranged as a ring oscillator (14) comprises at least one delay element (27 to 31) included in a closed circuit. At least one delay element (27 to 30) has at least two different adjustable delay times. A controller (19) is provided for setting the delay times of at least one delay element (27 to 30) in dependence on the comparison signal.