Abstract: A memory system includes a memory stack including a number of memory dies interconnected via copper bonding, a logic die coupled to the memory stack via a copper bonding. The memory system further includes a buffer die extended to provide the copper bonding between the logic die and the memory stack and a silicon carrier layer bonded to the memory stack and the logic die.

Abstract: Copper-connected glass modules on a glass board are provided. An apparatus includes one or more dies, an interposer formed of a first material, the interposer coupled to the one or more silicon dies, the interposer comprising an interconnection layer formed on one side of the interposer, wherein the interconnection layer includes a plurality of copper interconnects, and a substrate comprising a top layer, glass core, and a bottom layer, wherein the interconnection layer of the interposer and the top layer of the substrate are copper bonded.

Abstract: A memory system includes a memory stack including a number of memory dies interconnected via copper bonding, a logic die coupled to the memory stack via a copper bonding. The memory system further includes a buffer die extended to provide the copper bonding between the logic die and the memory stack and a silicon carrier layer bonded to the memory stack and the logic die.

Abstract: A memory system includes a memory stack including a number of memory dies interconnected via copper bonding, a logic die coupled to the memory stack via a copper bonding. The memory system further includes a buffer die extended to provide the copper bonding between the logic die and the memory stack and a silicon carrier layer bonded to the memory stack and the logic die.

Abstract: A transistor module includes a substrate; a transistor on the substrate; a dielectric layer disposed over the transistor and the substrate; a metal layer disposed over the dielectric layer and the transistor, the metal layer contacting a portion of the transistor; a metal pillar disposed over the metal layer; and a dielectric cushion disposed between the metal layer and the metal pillar over the transistor. The dielectric cushion includes dielectric material that is softer than the metal pillar, for reducing strain on semiconductor junctions when at least one of tensile or compressive stress is exerted on the metal pillar with respect to the substrate. The transistor module may further include at least one buttress formed between the metal layer and the substrate, adjacent to the transistor, for further reducing strain on the semiconductor junctions by providing at least one corresponding alternative stress path that substantially bypasses the transistor.

Abstract: A transistor module includes a substrate; a transistor on the substrate; a dielectric layer disposed over the transistor and the substrate; a metal layer disposed over the dielectric layer and the transistor, the metal layer contacting a portion of the transistor; a metal pillar disposed over the metal layer; and a dielectric cushion disposed between the metal layer and the metal pillar over the transistor. The dielectric cushion includes dielectric material that is softer than the metal pillar, for reducing strain on semiconductor junctions when at least one of tensile or compressive stress is exerted on the metal pillar with respect to the substrate. The transistor module may further include at least one buttress formed between the metal layer and the substrate, adjacent to the transistor, for further reducing strain on the semiconductor junctions by providing at least one corresponding alterative stress path that substantially bypasses the transistor.

Abstract: A method of fabricating Group III-V semiconductor metal oxide semiconductor (MOS) and III-V MOS devices are described.

Abstract: A method of fabricating Group III-V semiconductor metal oxide semiconductor (MOS) and III-V MOS devices are described.

Abstract: A three-dimensional pixel array, a method of manufacturing a pixel array and an imager including the three-dimensional pixel array. The three-dimensional array includes multiple groups of pixels, each group of pixels including a first layer and a second layer. The first layer includes multiple photosensitive elements, one per pixel in the group, at least one floating diffusion region connected to each photosensitive element in the group via at least one respective transfer gate per pixel and multiple transfer gate lines, at least two transfer gate lines connected to each respective transfer gate in each row of pixels. The second layer includes at least a rest transistor per group and a source follower transistor coupled to the shared floating diffusion in the first layer.

Abstract: An apparatus and method for identifying aberrant pixels in an image sensor. The apparatus includes a light sensitive element configured to detect a first signal value representing a first level of an incident light and a light sensitive region separate from the light sensitive element configured to detect a second signal value representing a second level of the incident light. Comparing circuitry is configured to compare the first signal value and the second signal value and to output a signal indicating the pixel is an aberrant pixel if the first and second signal values differ by more than a maximum threshold value or less than a minimum threshold value in a threshold value range.

Abstract: A three-dimensional pixel array, a method of manufacturing a pixel array and an imager including the three-dimensional pixel array. The three-dimensional array includes multiple groups of pixels, each group of pixels including a first layer and a second layer. The first layer includes multiple photosensitive elements, one per pixel in the group, at least one floating diffusion region connected to each photosensitive element in the group via at least one respective transfer gate per pixel and multiple transfer gate lines, at least two transfer gate lines connected to each respective transfer gate in each row of pixels. The second layer includes at least a rest transistor per group and a source follower transistor coupled to the shared floating diffusion in the first layer.

Abstract: A method of constructing a backside illuminated image sensor is described. The method includes the steps of forming a semiconductor wafer, forming at least electrical contacts in the semiconductor wafer, forming, in a handle wafer separate from the semiconductor wafer, a plurality of via holes, attaching the semiconductor wafer to the handle wafer such that the via holes in the handle wafer are aligned with the respective electrical contacts on the semiconductor wafer, removing the substrate layer from the semiconductor wafer, removing at least a portion of the handle wafer to expose the plurality of via holes, filling each of the exposed via holes with a conductive material and applying a solder material to each of the exposed via holes such that the conductive material in each of the via holes is electrically connected to the solder material.

Abstract: An apparatus and method for identifying aberrant pixels in an image sensor. The apparatus includes a light sensitive element configured to detect a first signal value representing a first level of an incident light and a light sensitive region separate from the light sensitive element configured to detect a second signal value representing a second level of the incident light. Comparing circuitry is configured to compare the first signal value and the second signal value and to output a signal indicating the pixel is an aberrant pixel if the first and second signal values differ by more than a maximum threshold value or less than a minimum threshold value in a threshold value range.

Abstract: A pixel sensor cell includes a substrate of a first conductivity type, and a photoconversion region. The photoconversion region includes a pinning layer of the first conductivity type for receiving incident light of multiple colors, and a diode implant layer of a second conductivity type, disposed below the pinning layer, for accumulating photo-generated charge. Also included is a deep well of the first conductivity type, disposed below the diode implant layer, for rejecting at least one color of the incident light. The deep well includes a doped region, vertically disposed at a predetermined depth below the diode implant layer. The diode implant layer is effective in accumulating photo-generated charge of a blue color, and the deep well is effective in rejecting photo-generated charges of green and red colors from the diode implant layer.

Abstract: A method of fabricating Group III-V semiconductor metal oxide semiconductor (MOS) and III-V MOS devices are described.