Abstract: An apparatus for performing arbitration increases the fairness of arbitrations, decreases system latency, increases system throughput, and is suitable for use in more complex systems. According to an exemplary embodiment, the apparatus includes a generator for generating a plurality of arbitration numbers corresponding to a plurality of agents, and circuitry for selecting one of the agents to access a resource shared by the agents based on the arbitration numbers. At least one of the arbitration numbers includes a plurality of fields corresponding to a plurality of parameters.

Abstract: A television receiver includes a source of digital data comprising a plurality of data streams each representing one of a standard definition television signal and a high definition television signal and encoded in such a manner that it may be decoded at full resolution to produce an image substantially without visible decoding artifacts or decoded at partial resolution to produce an image possibly including visible decoding artifacts. A decoder is coupled to the digital data source, and has a maximum decoding bandwidth less than that required to simultaneously decode two high definition television signals at full decoding resolution. A controller, is coupled to the decoder, for selecting two respective ones of the data streams responsive to user input, and if both represent a high definition television signal, requesting user input for specifying one of the two respective data streams to decode at partial resolution.

Abstract: A method and apparatus for simultaneously recording and displaying video signals from two different video sources. The apparatus comprises a main channel processing circuit, a second channel processing circuit, and common circuitry. The common circuit comprises a digital video decoder pipe that decodes both first and second encoded video signals. A PIP picture is produced using a common reference clock that is derived from the first video signal. In a record mode, a second channel clock reference is coupled to the second channel processing circuit to produce a recordable signal using a digital encoder. The recordable signal also forms a PIP picture that is coupled to the main channel processing circuit to produce a PIP picture that is used to monitor the recording process.

Abstract: An adaptive transport protocol decoder includes a source of a stream of packets, each including a payload, and having a first transport protocol, and a source of a stream of packets, each including a payload, and having a second transport protocol. A protocol decoder, coupled to the first and second packet stream sources, extracts the respective payloads from the packets from a selected one of the first and second packet stream sources.

Abstract: A method and apparatus for simultaneously recording and displaying video signals from two different video sources. The apparatus comprises a main channel processing circuit/logic, a second channel processing circuit/logic, and common circuitry/logic. The common circuitry comprises a digital video encoder pipe that decodes both a first and second encoded video signals. The main channel processing circuit processes a first decoded video signal utilizing a first clock to form a main picture for display. The second channel processing circuit processes a second decoded video signal to form a PIP picture for combination with the main picture for display. The PIP picture is produced using a second clock signal that is independent from the first clock signal. In a record mode, the second channel clock is coupled to the second channel processing circuit to produce a recordable signal using a digital encoder.

Abstract: A vertical blanking interval (VBI) encoder for providing VBI encoded data supports a “RAW mode” of operation. In particular, the VBI encoder comprises a first FIFO (first-in, first-out) buffer for providing service data to be VBI encoded, and a second FIFO for specifying VBI format data.

Abstract: A server apparatus receives packetized data and transmits the packetized data over a network. The apparatus includes an input for receiving the packetized data from a signal source. An AC clock counter receives an AC power signal and generates a count value in dependence upon a frequency of the AC power signal. An output is coupled to the network and transmits the packetized data and the count value to a client device. A clock associated with the client device is controlled in dependence upon the count value.

Abstract: A method and an apparatus using a system level clocking scheme to remove jitter from multi-media packets distributed over an asynchronous network, in particular an asynchronous network. The present invention overcomes the problems associated with jitter introduced in an asynchronous network by using various time stamps to synchronize a client device clock to a headend clock and to control the data flow in the client device to match the rate that the data is received by a broadband receiver coupled to the headend. A first time stamp is prepended to the transport packets when the packets are received from the headend. A second time stamp is placed in the data frame when the data frame is placed on the network. A third time stamp is placed in the data frame when the data frame is received from the network. The second and third time stamps are used for synchronizing the client clock to the server clock, which is in turn frequency locked to the headend clock.

Abstract: A method and an apparatus using a system level clocking scheme to remove jitter from multi-media packets distributed over an asynchronous network. The present invention overcomes the problems associated with jitter introduced in an asynchronous network by using various time stamps to synchronize a client device clock to a headend clock and to control the data flow in the client device to match the rate that the data is received by a broadband receiver coupled to the headend. The present invention allows the client device to synchronize to a selected one of a plurality of headend clock by including a clock adjustment factor along with the time stamps. The time stamps are added at the physical layer so that the time stamps correspond to the time the data packets are placed onto and received from the asynchronous network.

Abstract: There is provided a serial compressed bus interface having a reduced pin count. The interface includes a serial-to-parallel converter having a single serial data input line adapted to receive time-division multiplexed serial data from a plurality of data sources. Enable logic is adapted to input at least one data valid signal that identifies each of a plurality of data consumers for which the time-division multiplexed serial data is valid.

Abstract: A method and apparatus for identifying a false MPEG-2 packet synchronization lock condition by parsing MPEG-2 packets that may have been incorrectly delineated by a sync-byte checksum-decoder, to detect resulting anomalies. Forcing the restart of the conventional checksum-encoded sync-byte synchronization/lock process upon generating a “resync” command based upon the anomalies detected by a False Lock Detector. Reliably synchronizing and delivering the MPEG-2 stream to the receiver transport layer. The False-Lock Detector circuit compares the content of the currently identified packet header or payload portion of a sync-byte delineated packet with expected values in order to detect a false-lock condition and to eliminate false sync-byte position-candidates from the basis of a “synchronization lock”.

Abstract: A data storage element comprising a substrate and a data track disposed on the substrate, the data track comprising a plurality of data sectors, each of the data sectors being formatted in accordance with a first digital data standard and comprised of a control data portion and a payload data portion, each of the payload portions including a plurality of data packets formatted in accordance with a digital television standard. In particular, the data packs correspond to program stream packs specified in the DVD standard and the data packets correspond to transport packets specified in the ATSC standard. The present storage element enables the data stored thereon to be read by a conventional DVD front end and provided to an ATSC receiver without processing the contents of the transport packets. Therefore, the present invention allows ATSC data to be stored on a DVD disc and to be provided in a manner that can fully realize the display capabilities of the ATSC receiver.

Abstract: A method and a system for performing trick mode features in a personal video recorder without introducing a channel change delay during normal viewing. The method includes the steps of recording a video source signal and concurrently bypassing the video source signal to a display device, without experiencing any buffering delay associated with the recording step. During trick mode operation the bypassing step can be automatically terminated and a recorded version of the video source signal can be substituted and sent to the display. The bypassing step further can include substituting, without any buffering delay, an alternate video source signal in response to a user selection of an alternate video source signal channel. A user notification can be generated to acknowledge receipt of a trick mode command. The user notification can be terminated once the step of substituting the recorded version of the video source signal has been completed.

Abstract: A method for dynamic contrast improvement of video data includes the steps of analyzing a portion of a video frame, and forcing a start of DCI transfer function computations in response to an end of the analysis of the portion of the video frame.

Abstract: An improved image processing system involves decoding compressed image data including frequency domain coefficients defining blocks of pixel values representing an image at a first resolution to provide an image at a reduced second resolution for display from a selected sub-set of the frequency domain coefficients. The apparatus includes an enhanced motion-compensation-unit (MCU) operating with blocks of pixel values representing an image at an intermediate third resolution lower than the first resolution but higher than the reduced second resolution.

Abstract: A method for dynamic contrast improvement of video data includes the steps of analyzing a portion of a video frame, and forcing a start of DCI transfer function computations in response to an end of the analysis of the portion of the video frame.

Abstract: A server apparatus receives packetized data and transmits the packetized data over a network. The apparatus includes an input for receiving the packetized data from a signal source. An AC clock counter receives an AC power signal and generates a count value in dependence upon a frequency of the AC power signal. An output is coupled to the network and transmits the packetized data and the count value to a client device. A clock associated with the client device is controlled in dependence upon the count value.

Abstract: A method and an apparatus using a system level clocking scheme to remove jitter from multi-media packets distributed over an asynchronous network, in particular an asynchronous network. The present invention overcomes the problems associated with jitter introduced in an asynchronous network by using various time stamps to synchronize a client device clock to a headend clock and to control the data flow in the client device to match the rate that the data is received by a broadband receiver coupled to the headend. A first time stamp is prepended to the transport packets when the packets are received from the headend. A second time stamp is placed in the data frame when the data frame is placed on the network. A third time stamp is placed in the data frame when the data frame is received from the network. The second and third time stamps are used for synchronizing the client clock to the server clock, which is in turn frequency locked to the headend clock.

Abstract: A method and an apparatus using a system level clocking scheme to remove jitter from multi-media packets distributed over an asynchronous network. The present invention overcomes the problems associated with jitter introduced in an asynchronous network by using various time stamps to synchronized a client device clock to a headend clock and to control the data flow in the client device to match the rate that the data is received by a broadband receiver coupled to the headend. The present invention allows the client device to synchronize to a selected one of a plurality of headend clock by including a clock adjustment factor along with the time stamps. The time stamps are added at the physical layer so that the time stamps correspond to the time the data packets are placed onto and received from the asynchronous network.

Abstract: A method and apparatus for simultaneously recording and displaying video signals from two different video sources. The apparatus comprises a main channel processing circuit (148), a second channel processing circuit (150), and common circuitry (152). The common circuit comprises a digital video decoder pipe (112) that decodes both first and second encoded video signals. A PIP picture is produced using a common reference clock that is derived from the first video signal. In a record mode, a second channel clock reference is coupled to the second channel processing circuit to produce a recordable signal using a digital encoder. The recordable signal also forms a PIP picture that is coupled to the main channel processing circuit to produce a PIP picture that is used to monitor the recording process.