Abstract: A flip chip device and methods for fabrication are provided. An interconnect layer for a device include a plurality of solder bumps arranged within the interconnect layer. A first subset of the plurality of solder bumps has a first cross-sectional area, where the first subset is arranged along a first position at a first edge of the interconnect layer. A second subset of the plurality of solder bumps has a second cross-sectional area, where the second subset is arranged at a second position of the interconnect layer. A third subset of the plurality of solder bumps is arranged between the first position and the second position, where the third subset has a plurality of cross-sectional areas.

Abstract: An integrated circuit package structure is provided that includes a chip carrier substrate, at least one processor die provided on the chip carrier substrate, a plurality of lateral escape wiring lines connected to and extending away from the at least one processor die, and a plurality of chips at least partially surrounding the processor die, at least one of the chips overlapping with at least one of the lateral escape wiring lines in a plan view. An interconnect structure of the chips includes at least one vertical power feed structure that is configured and positioned not to intersect with the lateral escape wiring lines in the plan view.

Abstract: A flip chip device and methods for fabrication are provided. An interconnect layer for a device include a plurality of solder bumps arranged within the interconnect layer. A first subset of the plurality of solder bumps has a first cross-sectional area, where the first subset is arranged along a first position at a first edge of the interconnect layer. A second subset of the plurality of solder bumps has a second cross-sectional area, where the second subset is arranged at a second position of the interconnect layer. A third subset of the plurality of solder bumps is arranged between the first position and the second position, where the third subset has a plurality of cross-sectional areas.

Abstract: An integrated circuit package structure is provided that includes a chip carrier substrate, at least one processor die provided on the chip carrier substrate, a plurality of lateral escape wiring lines connected to and extending away from the at least one processor die, and a plurality of chips at least partially surrounding the processor die, at least one of the chips overlapping with at least one of the lateral escape wiring lines in a plan view. An interconnect structure of the chips includes at least one vertical power feed structure that is configured and positioned not to intersect with the lateral escape wiring lines in the plan view.

Abstract: An electrically insulating substrate is provided. The electrically insulating substrate includes a set of areas to be formed into a set of printed circuit boards. Each of the set of areas is separated from others of the set of areas by a dicing channel. A set of signal wiring conductors is fabricated onto the set of areas of the electrically insulating substrate so that at least one of the set of signal wiring conductors terminates proximate to the dicing channel. A set of plated through holes is fabricated through at least one of the set of areas such that at least one of the set of plated through holes connects to at least one of the set of signal wiring conductors. The electrically insulating substrate is singulated along a set of singulation lines to form the set of printed circuit boards. The singulation lines intersect with the plated through holes, so that a portion of the plated through holes is exposed along the peripheral edge of the resulting printed circuit boards.

Abstract: An improved electronic module assembly and method of fabrication is disclosed. A patterned array of adhesive is deposited on a laminate, to which a chip is attached. Each region of adhesive is referred to as a lid tie. A lid is placed on the laminate, and is in contact with the lid ties. The lid ties serve to add stability to the laminate and reduce flexing during thermal processing and mechanical stress.

Abstract: An improved electronic module assembly and method of fabrication is disclosed. A patterned array of adhesive is deposited on a laminate, to which a chip is attached. Each region of adhesive is referred to as a lid tie. A lid is placed on the laminate, and is in contact with the lid ties. The lid ties serve to add stability to the laminate and reduce flexing during thermal processing and mechanical stress.

Abstract: An improved electronic module assembly and method of fabrication is disclosed. A patterned array of adhesive is deposited on a laminate, to which a chip is attached. Each region of adhesive is referred to as a lid tie. A lid is placed on the laminate, and is in contact with the lid ties. The lid ties serve to add stability to the laminate and reduce flexing during thermal processing and mechanical stress.

Abstract: An improved electronic module assembly and method of fabrication is disclosed. A patterned array of adhesive is deposited on a laminate, to which a chip is attached. Each region of adhesive is referred to as a lid tie. A lid is placed on the laminate, and is in contact with the lid ties. The lid ties serve to add stability to the laminate and reduce flexing during thermal processing and mechanical stress.

Abstract: An electrically insulating substrate is provided. The electrically insulating substrate includes a set of areas to be formed into a set of printed circuit boards. Each of the set of areas is separated from others of the set of areas by a dicing channel. A set of signal wiring conductors is fabricated onto the set of areas of the electrically insulating substrate so that at least one of the set of signal wiring conductors terminates proximate to the dicing channel. A set of plated through holes is fabricated through at least one of the set of areas such that at least one of the set of plated through holes connects to at least one of the set of signal wiring conductors. The electrically insulating substrate is singulated along a set of singulation lines to form the set of printed circuit boards. The singulation lines intersect with the plated through holes, so that a portion of the plated through holes is exposed along the peripheral edge of the resulting printed circuit boards.

Abstract: A burnisher for disassociating undesirable material from a work piece includes a wire and a burnishing medium operably associated with the wire. The flexibility of the burnisher permits forces to be generated to disassociate the burnishing medium.