Abstract: A small number of redundant circuits are freely allocable to any of a plurality of partitions or systems within an integrated circuit, such as a large dynamic random access memory (DRAM) consistent with the provision of parallel simultaneous refresh of corresponding addresses in all partitions or systems thereof. A valid address of a redundant circuit substituted for a partial address of a circuit in any partition or system is detected to disable refresh of that address in all partitions. The partition in which the substitution has been made is sensed and the disablement of refresh of all other partitions is overridden so that all partitions or systems in which a substitution has not been made may be refreshed concurrently with the substituted redundant circuit.