Patents by Inventor Thomas Edwin Frisinger

Thomas Edwin Frisinger has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12008677
    Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for compatible compression for different types of image views. A graphics processor may select a first common format of a plurality of common formats for at least one image based on at least one of application data or first metadata associated with the at least one image. The graphics processor may encode the at least one image based on the selected first common format for the at least one image. The graphics processor may select a second common format for the at least one image based on second metadata of the at least one image. The second common format may be identical to the first common format. The graphics processor may decode the at least one image based on the selected second common format for the at least one image.
    Type: Grant
    Filed: March 17, 2022
    Date of Patent: June 11, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Srihari Babu Alla, Tao Wang, Andrew Evan Gruber, Matthew Netsch, Richard Hammerstone, Thomas Edwin Frisinger
  • Patent number: 12002142
    Abstract: The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may process a first workload of a plurality of workloads at each of multiple clusters in a GPU pipeline. The apparatus may also increment a plurality of performance counters during the processing of the first workload at each of the multiple clusters. Further, the apparatus may determine, at each of the multiple clusters, whether the first workload is finished processing. The apparatus may also read, upon determining that the first workload is finished processing, a value of each of the multiple clusters for each of the plurality of performance counters. Additionally, the apparatus may transmit an indication of the read value of each of the multiple clusters for all of the plurality of performance counters.
    Type: Grant
    Filed: July 12, 2021
    Date of Patent: June 4, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Tushar Garg, Thomas Edwin Frisinger, Nigel Poole, Vishwanath Shashikant Nikam, Vijay Kumar Donthireddy
  • Publication number: 20230343016
    Abstract: The present disclosure relates to graphics processing. An apparatus of the present disclosure may determine visibility streams corresponding to a target and a set of bins into which the target is divided. The apparatus may select one of a first rendering mode or a second rendering mode for the target based on the first visibility stream and based on the set of second visibility streams. When the first rendering mode is select, the apparatus may configure each of the set of bins into a first subset associated with a first type of rendering pass or a second subset associated with a second type of rendering pass. The apparatus may then render the target based on the selected one of the first rendering mode or the second rendering mode and, if applicable, based on the first rendering pass type or the second rendering pass type.
    Type: Application
    Filed: November 18, 2020
    Publication date: October 26, 2023
    Inventors: Srihari Babu ALLA, Jonnala Gadda NAGENDRA KUMAR, Avinash SEETHARAMAIAH, Andrew Evan GRUBER, Thomas Edwin FRISINGER, Richard HAMMERSTONE, Bo DU, Yongjun XU
  • Publication number: 20230298123
    Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for compatible compression for different types of image views. A graphics processor may select a first common format of a plurality of common formats for at least one image based on at least one of application data or first metadata associated with the at least one image. The graphics processor may encode the at least one image based on the selected first common format for the at least one image. The graphics processor may select a second common format for the at least one image based on second metadata of the at least one image. The second common format may be identical to the first common format. The graphics processor may decode the at least one image based on the selected second common format for the at least one image.
    Type: Application
    Filed: March 17, 2022
    Publication date: September 21, 2023
    Inventors: Srihari Babu ALLA, Tao WANG, Andrew Evan GRUBER, Matthew NETSCH, Richard HAMMERSTONE, Thomas Edwin FRISINGER
  • Publication number: 20230290034
    Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for fast incremental shared constants. In aspects, a CPU may determine/update shared constant data for a first draw call of a plurality of draw calls. The shared constant data, which may correspond to at least one shader, may be updated based on a draw call update for the first draw call. The CPU may communicate the updated shared constant data for the first draw call to a GPU. The GPU may receive, in at least one register, the updated shared constant data from the CPU and configure the at least one register based on the updated shared constant data corresponding to the draw call update of the first draw call of the plurality of draw calls.
    Type: Application
    Filed: May 15, 2023
    Publication date: September 14, 2023
    Inventors: Thomas Edwin FRISINGER, Richard HAMMERSTONE, Andrew Evan GRUBER, Gang ZHONG, Yun DU, Jonnala Gadda NAGENDRA KUMAR
  • Patent number: 11694384
    Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for fast incremental shared constants. In aspects, a CPU may determine/update shared constant data for a first draw call of a plurality of draw calls. The shared constant data, which may correspond to at least one shader, may be updated based on a draw call update for the first draw call. The CPU may communicate the updated shared constant data for the first draw call to a GPU. The GPU may receive, in at least one register, the updated shared constant data from the CPU and configure the at least one register based on the updated shared constant data corresponding to the draw call update of the first draw call of the plurality of draw calls.
    Type: Grant
    Filed: October 30, 2020
    Date of Patent: July 4, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Thomas Edwin Frisinger, Richard Hammerstone, Andrew Evan Gruber, Gang Zhong, Yun Du, Jonnala Gadda Nagendra Kumar
  • Publication number: 20230019763
    Abstract: The present disclosure relates to methods and apparatus for graphics processing. For example, disclosed techniques facilitate improving bindless state processing at a graphics processor. Aspects of the present disclosure can receive, at a graphics processor, a shader program including a preamble section and a main instructions section. Aspects of the present disclosure can also execute, with a scalar processor dedicated to processing preamble sections, instructions of the preamble section to implement a bindless mechanism for loading constant data associated with the shader program. Additionally, aspects of the present disclosure can distribute the main instructions section and the constant data to a streaming processor for executing the shader program.
    Type: Application
    Filed: January 31, 2020
    Publication date: January 19, 2023
    Inventors: Yun DU, Andrew Evan GRUBER, Chun YU, Chihong ZHANG, Thomas Edwin FRISINGER, Richard HAMMERSTONE, Zilin YING, Heng QI, Quanquan XU, Sheng GU
  • Publication number: 20230009205
    Abstract: The present disclosure relates to methods and devices for graphics processing including an apparatus, e.g., a GPU. The apparatus may process a first workload of a plurality of workloads at each of multiple clusters in a GPU pipeline. The apparatus may also increment a plurality of performance counters during the processing of the first workload at each of the multiple clusters. Further, the apparatus may determine, at each of the multiple clusters, whether the first workload is finished processing. The apparatus may also read, upon determining that the first workload is finished processing, a value of each of the multiple clusters for each of the plurality of performance counters. Additionally, the apparatus may transmit an indication of the read value of each of the multiple clusters for all of the plurality of performance counters.
    Type: Application
    Filed: July 12, 2021
    Publication date: January 12, 2023
    Inventors: Tushar GARG, Thomas Edwin FRISINGER, Nigel POOLE, Vishwanath Shashikant NIKAM, Vijay Kumar DONTHIREDDY
  • Patent number: 11373267
    Abstract: The present disclosure relates to methods and apparatus for graphics processing. Aspects of the present disclosure can determine a portion of a display area, where the portion of the display area is determined based on display content of the display area. Further, aspects of the present disclosure can communicate display information corresponding to the determined portion of the display area. Additionally, aspects of the present disclosure can update the display information corresponding to the determined portion of the display area. Aspects of the present disclosure can also communicate the updated display information corresponding to the determined portion of the display area. Aspects of the present disclosure can also render at least some display content of the display area corresponding to the determined portion of the display area. In some aspects, the updated display information can be based on the rendered display content of the display area.
    Type: Grant
    Filed: November 4, 2019
    Date of Patent: June 28, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Tao Wang, Shambhoo Khandelwal, Andrew Evan Gruber, Shangmei Yu, Jing Gao, Junmei Shao, Thomas Edwin Frisinger, Rick Hammerstone
  • Patent number: 11373268
    Abstract: The present disclosure relates to methods and apparatus for hybrid rendering of video/graphics content by a graphics processing unit. The apparatus can configure the graphics processing unit of a display apparatus to perform multiple rendering passes for a frame of a scene to be displayed on a display device. Moreover, the apparatus can control the graphics processing unit to perform a first rendering pass of the multiple rendering passes to generate a first render target that is stored in either an on-chip graphics memory of the GPU or a system of the display apparatus. The apparatus can also control the graphics processing unit to perform a second rendering pass to generate a second render target that is alternatively stored in the system memory of the display apparatus or on-chip graphics memory of the GPU.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: June 28, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Srihari Babu Alla, Jonnala Gadda Nagendra Kumar, Avinash Seetharamaiah, Andrew Evan Gruber, Richard Hammerstone, Thomas Edwin Frisinger, Daniel Archard
  • Publication number: 20220139021
    Abstract: This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for fast incremental shared constants. In aspects, a CPU may determine/update shared constant data for a first draw call of a plurality of draw calls. The shared constant data, which may correspond to at least one shader, may be updated based on a draw call update for the first draw call. The CPU may communicate the updated shared constant data for the first draw call to a GPU. The GPU may receive, in at least one register, the updated shared constant data from the CPU and configure the at least one register based on the updated shared constant data corresponding to the draw call update of the first draw call of the plurality of draw calls.
    Type: Application
    Filed: October 30, 2020
    Publication date: May 5, 2022
    Inventors: Thomas Edwin FRISINGER, Richard HAMMERSTONE, Andrew Evan GRUBER, Gang ZHONG, Yun DU, Jonnala Gadda NAGENDRA KUMAR
  • Patent number: 11321804
    Abstract: Methods, systems, and devices for graphics processer unit (GPU) operations are described. A device may monitor one or more states of a GPU during a duration. Based on monitoring the one or more GPU states, the device may determine an execution of a GPU command that is common to at least two GPU operations for clearing the GPU buffer. The device may determine whether the GPU clear command has previously been executed during a duration or a GPU cycle in which the device monitored the GPU states. The device may process the GPU clear command based on the determination of whether the GPU clear command has previously been executed. For example, the device may drop the GPU clear command based on the determination or modify a portion of the GPU clear command and execute at least the modified portion of the GPU clear command.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: May 3, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Thomas Edwin Frisinger, Richard Hammerstone, Jonnala Gadda Nagendra Kumar, Avinash Seetharamaiah, Shangmei Yu, Srihari Babu Alla
  • Publication number: 20220122214
    Abstract: Methods, systems, and devices for graphics processer unit (GPU) operations are described. A device may monitor one or more states of a GPU during a duration. Based on monitoring the one or more GPU states, the device may determine an execution of a GPU command that is common to at least two GPU operations for clearing the GPU buffer. The device may determine whether the GPU clear command has previously been executed during a duration or a GPU cycle in which the device monitored the GPU states. The device may process the GPU clear command based on the determination of whether the GPU clear command has previously been executed. For example, the device may drop the GPU clear command based on the determination or modify a portion of the GPU clear command and execute at least the modified portion of the GPU clear command.
    Type: Application
    Filed: October 15, 2020
    Publication date: April 21, 2022
    Inventors: Thomas Edwin Frisinger, Richard Hammerstone, Jonnala Gadda Nagendra Kumar, Avinash Seetharamaiah, Shangmei Yu, Srihari Babu Alla
  • Publication number: 20220101479
    Abstract: The present disclosure relates to methods and apparatus for hybrid rendering of video/graphics content by a graphics processing unit. The apparatus can configure the graphics processing unit of a display apparatus to perform multiple rendering passes for a frame of a scene to be displayed on a display device. Moreover, the apparatus can control the graphics processing unit to perform a first rendering pass of the multiple rendering passes to generate a first render target that is stored in either an on-chip graphics memory of the GPU or a system of the display apparatus. The apparatus can also control the graphics processing unit to perform a second rendering pass to generate a second render target that is alternatively stored in the system memory of the display apparatus or on-chip graphics memory of the GPU.
    Type: Application
    Filed: September 30, 2020
    Publication date: March 31, 2022
    Inventors: Srihari Babu ALLA, Jonnala Gadda NAGENDRA KUMAR, Avinash SEETHARAMAIAH, Andrew Evan GRUBER, Richard HAMMERSTONE, Thomas Edwin FRISINGER, Daniel ARCHARD
  • Patent number: 11176734
    Abstract: The present disclosure relates to methods and apparatus for graphics processing. An example method generally includes receiving, at a graphics processing unit (GPU), a plurality of commands corresponding to a plurality of draws across a frame, each of the plurality of commands indicating a depth test direction with respect to a low-resolution depth (LRZ) buffer for the corresponding draw. The method generally includes maintaining, at the GPU, a LRZ status buffer to store a corresponding depth test direction for a first command in time of the plurality of commands processed by the GPU. The method generally includes disabling, at the GPU, use of the LRZ buffer for depth testing for any of the plurality of commands remaining unprocessed after processing a command of the plurality of commands having a different depth test direction than the corresponding depth test direction stored in the LRZ status buffer.
    Type: Grant
    Filed: October 6, 2020
    Date of Patent: November 16, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Srihari Babu Alla, Adimulam Ramesh Babu, Jonnala Gadda Nagendra Kumar, Avinash Seetharamaiah, Tao Wang, Xuefeng Tang, Thomas Edwin Frisinger, Andrew Evan Gruber
  • Publication number: 20210133912
    Abstract: The present disclosure relates to methods and apparatus for graphics processing. Aspects of the present disclosure can determine a portion of a display area, where the portion of the display area is determined based on display content of the display area. Further, aspects of the present disclosure can communicate display information corresponding to the determined portion of the display area. Additionally, aspects of the present disclosure can update the display information corresponding to the determined portion of the display area. Aspects of the present disclosure can also communicate the updated display information corresponding to the determined portion of the display area. Aspects of the present disclosure can also render at least some display content of the display area corresponding to the determined portion of the display area. In some aspects, the updated display information can be based on the rendered display content of the display area.
    Type: Application
    Filed: November 4, 2019
    Publication date: May 6, 2021
    Inventors: Tao WANG, Shambhoo KHANDELWAL, Andrew Evan GRUBER, Shangmei YU, Jing GAO, Junmei SHAO, Thomas Edwin Frisinger, Rick Hammerstone
  • Publication number: 20200013137
    Abstract: Methods, systems, and devices for rendering are described. A device may divide a frame into a plurality of bins. The device may generate a command stream containing multiple repetitions of a fixed-stride draw table (FSDT), where each repetition of the FSDT includes a respective state vector for one or more hardware registers of a set of hardware registers. The device may identify, for each bin, a subset of the multiple repetitions of the FSDT in the command stream that include a live draw call. The device may execute, using the set of hardware registers, one or more rendering commands for each bin based at least in part on the corresponding subset of the multiple repetitions of the FSDT.
    Type: Application
    Filed: July 5, 2018
    Publication date: January 9, 2020
    Inventors: Richard Hammerstone, Nigel Poole, Thomas Edwin Frisinger, Andrew Evan Gruber, Anisha Datla
  • Patent number: 10157443
    Abstract: The techniques of this disclosure include deferred batching of incremental constant loads. Graphics APIs include the ability to use lightweight constants for use by shaders. A buffer is allocated by a graphics processing unit (GPU) driver that contains a snapshot of the current lightweight constants. This may provide a complete set of state to serve as a starting point. From then on updates to the lightweight constants may be appended to this buffer in an incremental fashion by inserting the update and increasing the size of the buffer by a command processor on a graphics processing unit (GPU). The incremental nature of the updates may be captured, but removes the need for issuing them on every draw call and instead the incremental updates may be batch processed when a live draw call is encountered.
    Type: Grant
    Filed: July 28, 2017
    Date of Patent: December 18, 2018
    Assignee: QUALCOMM Incorporated
    Inventors: Richard Hammerstone, Thomas Edwin Frisinger, Andrew Evan Gruber, Nigel Terence Poole
  • Patent number: 9489313
    Abstract: The present disclosure provides for systems and methods to process a non-resident page that may include attempting to access the non-resident page, an address for the non-resident page pointing to a memory page containing default values, determining that the non-resident page should not cause a page fault based on an indicator indicating that a particular non-resident page should not generate a page fault, returning an indication that a memory read did not translate and returning the default value when the access of the non-resident page is a read and the non-resident page should not cause a page fault. Another example may discontinue a write when the access of the non-resident page is a write and the non-resident page should not cause a page fault.
    Type: Grant
    Filed: September 24, 2013
    Date of Patent: November 8, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: David A. Gotwalt, Thomas Edwin Frisinger, Andrew Evan Gruber, Eric Demers, Colin Christopher Sharp
  • Publication number: 20150089146
    Abstract: The present disclosure provides for systems and methods to process a non-resident page that may include attempting to access the non-resident page, an address for the non-resident page pointing to a memory page containing default values, determining that the non-resident page should not cause a page fault based on an indicator indicating that a particular non-resident page should not generate a page fault, returning an indication that a memory read did not translate and returning the default value when the access of the non-resident page is a read and the non-resident page should not cause a page fault. Another example may discontinue a write when the access of the non-resident page is a write and the non-resident page should not cause a page fault.
    Type: Application
    Filed: September 24, 2013
    Publication date: March 26, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: David A. Gotwalt, Thomas Edwin Frisinger, Andrew Evan Gruber, Eric Demers, Colin Christopher Sharp