Abstract: A microprocessor performs a fused multiply-accumulate operation of a form ±A*B±C using first and second execution units. An input operand analyzer circuit determines whether values of A, B and/or C meet a sufficient condition to perform a joint accumulation of C with partial products of A and B. The first instruction execution unit multiplies A and B and jointly accumulates C to partial products of A and B when the values of A, B and/or C meet a sufficient condition to perform a joint accumulation of C with the partial products of A and B. The second instruction execution unit separately accumulates C to the products of A and B when the values of A, B and/or C do not meet a sufficient condition to perform a joint accumulation of C with the partial products of A and B.

Abstract: A microprocessor comprises an instruction execution unit operable to generate an intermediate result vector and a plurality of calculation control indicators and storage external to the instruction execution unit which stores the intermediate result vector and the plurality of calculation control indicators. The intermediate result vector is generated from an application of at least a first arithmetic operation of a compound arithmetic operation. The calculation control indicators indicate how subsequent calculations to generate a final result from the intermediate result vector should proceed. The subsequent calculations may involve one or more remaining arithmetic operations of the compound arithmetic operation.

Abstract: A microprocessor comprises an instruction pipeline, a shared memory, and first and second arithmetic processing units in the instruction pipeline, each capable of reading or receiving operands from and writing or providing results to the shared memory. The first arithmetic processing unit performs a first portion of a mathematical operation to produce an intermediate result vector that is not a complete, final result of the mathematical operation. The first arithmetic processing unit generates a plurality of non-architectural calculation control indicators that indicate how subsequent calculations to generate a final result from the intermediate result vector should proceed. The second arithmetic processing unit performs a second portion of the mathematical operation, in accordance with the calculation control indicators, to produce a complete, final result of the mathematical operation.

Abstract: A microprocessor prepares a fused multiply-accumulate operation of a form ±A*B±C for execution by issuing first and second multiply-accumulate microinstructions to one or more instruction execution units to complete the fused multiply-accumulate operation. The first multiply-accumulate microinstruction causes an unrounded nonredundant result vector to be generated from a first accumulation of a selected one of (a) the partial products of A and B or (b) C with the partial products of A and B. The second multiply-accumulate microinstruction causes performance of a second accumulation of C with the unrounded nonredundant result vector, if the first accumulation did not include C. The second multiply-accumulate microinstruction also causes a final rounded result to be generated from the unrounded nonredundant result vector, wherein the final rounded result is a complete result of the fused multiply-accumulate operation.

Abstract: A microprocessor splits a fused multiply-accumulate operation of the form A*B+C into first and second multiply-accumulate sub-operations to be performed by a multiplier and an adder. The first sub-operation at least multiplies A and B, and conditionally also accumulates C to the partial products of A and B to generate an unrounded nonredundant sum. The unrounded nonredundant sum is stored in memory shared by the multiplier and adder for an indefinite time period, enabling the multiplier and adder to perform other operations unrelated to the multiply-accumulate operation. The second sub-operation conditionally accumulates C to the unrounded nonredundant sum if C is not already incorporated into the value, and then generates a final rounded result.

Abstract: Methods are provided for modifying hydrogenation catalysts having silica supports (or other non-alumina supports) with additional alumina, and using such catalysts to achieve unexpectedly superior hydrogenation of feedstocks. The modified hydrogenation catalysts can have a relatively low cracking activity while providing an increased activity for hydrogenation.

Abstract: A mixerless high frequency interferometric Doppler radar system and methods has been invented, numerically validated and experimentally tested. A continuous wave source, phase modulator (e.g., a continuously oscillating reference mirror) and intensity detector are utilized. The intensity detector measures the intensity of the combined reflected Doppler signal and the modulated reference beam. Rigorous mathematics formulas have been developed to extract bot amplitude and phase from the measured intensity signal. Software in Matlab has been developed and used to extract such amplitude and phase information from the experimental data. Both amplitude and phase are calculated and the Doppler frequency signature of the object is determined.

Abstract: A method of communicating with a shared imaging apparatus connected to a computer network, wherein communication over the network is facilitated through use of network packets, includes the steps of providing the shared imaging apparatus with networking hardware; providing the shared imaging apparatus with imaging apparatus firmware; defining a data channel associated with the networking hardware; instructing the networking hardware to accept information on the data channel from a user that owns the data channel; processing automatic Internet Protocol (IP) address negotiation network packets with the imaging apparatus firmware when the data channel is not owned; and processing second types of network packets, different from the automatic IP address negotiation network packets, by the networking hardware of the shared imaging apparatus when the data channel is owned.

Abstract: Systems and methods for the passive measurement of spectral lines from the absorption or emission by polar molecules. The system includes mmW front-end assembly, back-end electronics, and data acquisition hardware and software was assembled. The method relates to methods for processing multi-channel radiometric data from passive mmW detection systems.

Abstract: A method for negotiating an Internet Protocol (IP) address for an imaging apparatus connected to a network includes the steps of controlling network communication between the imaging apparatus and the network; defining an imaging state when the imaging apparatus is available for imaging, wherein during the imaging state the imaging apparatus waits in an idle state during periods of non-imaging; defining an automatic IP address negotiation state when the imaging apparatus is not available for imaging; if the imaging apparatus is in the idle state, then determining whether the imaging apparatus should leave the imaging state and enter the automatic IP address negotiation state; and when the imaging apparatus is in the automatic IP address negotiation state, then attempting to automatically assign an IP address to the imaging apparatus.

Abstract: A method for negotiating an Internet Protocol (IP) address for an imaging apparatus connected to a network includes the steps of controlling network communication between the imaging apparatus and the network; defining an imaging state when the imaging apparatus is available for imaging, wherein during the imaging state the imaging apparatus waits in an idle state during periods of non-imaging; defining an automatic IP address negotiation state when the imaging apparatus is not available for imaging; if the imaging apparatus is in the idle state, then determining whether the imaging apparatus should leave the imaging state and enter the automatic IP address negotiation state; and when the imaging apparatus is in the automatic IP address negotiation state, then attempting to automatically assign an IP address to the imaging apparatus.

Abstract: A method for negotiating an Internet Protocol (IP) address for an imaging apparatus connected to a network includes the steps of controlling network communication between the imaging apparatus and the network; defining an imaging state when the imaging apparatus is available for imaging, wherein during the imaging state the imaging apparatus waits in an idle state during periods of non-imaging; defining an automatic IP address negotiation state when the imaging apparatus is not available for imaging; if the imaging apparatus is in the idle state, then determining whether the imaging apparatus should leave the imaging state and enter the automatic IP address negotiation state; and when the imaging apparatus is in the automatic IP address negotiation state, then attempting to automatically assign an IP address to the imaging apparatus.

Abstract: A method of automatically assigning an internet protocol address to a device is provided. The method includes the steps of providing a network; providing a computer communicatively coupled to the network; providing a network adapter to communicatively couple the device to the network; the computer performing the steps of generating an internet protocol address; incorporating the internet protocol address in an address resolution protocol probe; sending the address resolution protocol probe on the network; and determining whether a response to the address resolution protocol probe indicates that the internet protocol address is in use; wherein if the internet protocol address is not in use, then performing the step of assigning the internet protocol address to the network adapter.

Abstract: A method of creating network printer ports on a computer workstation includes the steps of providing a network; communicatively coupling the computer workstation to the network; and communicatively coupling at least one printer to the network. The computer workstation performs the steps of transmitting a discovery packet to which a first printer of a designated type can respond; receiving a response packet from the first printer, the response packet including printer-specific network information of the first printer; identifying whether a network port exists for the first printer; and if no such network port exists, then creating a first network printer port for the first printer based on the printer-specific network information for the first printer.

Abstract: A processor capable of executing vector instructions includes at least an instruction sequencing unit and a vector processing unit that receives vector instructions to be executed from the instruction sequencing unit. The vector processing unit includes a plurality of multiply structures, each containing only a single multiply array, that each correspond to at least one element of a vector input operand. Utilizing the single multiply array, each of the plurality of multiply structures is capable of performing a multiplication operation on one element of a vector input operand and is also capable of performing a multiplication operation on multiple elements of a vector input operand concurrently. In an embodiment in which the maximum length of an element of a vector input operand is N bits, each of the plurality of multiply arrays can handle both N by N bit integer multiplication and M by M bit integer multiplication, where N is a non-unitary integer multiple of M.