Abstract: The semiconductor module is provided that includes a semiconductor housing and a plurality of integrated circuit dice positioned within the housing. The semiconductor module also includes a programmable memory device positioned within the housing and electrically coupled to the plurality of integrated circuit dice. The programmable memory device is programmable to identify the integrated circuit dice that meet a predetermined standard, such as an operating frequency requirement, or a core timing grade. Further, a method is provided for accessing a semiconductor module. The above mentioned housing is provided to enclose the plurality of integrated circuit dice and the programmable memory device. The integrated circuit dice of the plurality of integrated circuit dice that meet a predetermined standard are then identified. The programmable memory device is subsequently programmed to identify the selected integrated circuit dice.

Abstract: The semiconductor module is provided that includes a semiconductor housing and a plurality of integrated circuit dies positioned within the housing. The semiconductor module also includes a programmable memory device positioned within the housing and electrically coupled to the plurality of integrated circuit dies. The programmable memory device is programmable to identify the integrated circuit dies that meet a predetermined standard, such as an operating frequency requirement, or a core timing grade. Further, a method is provided for accessing a semiconductor module. The above mentioned housing is provided to enclose the plurality of integrated circuit dies and the programmable memory device. The integrated circuit dies of the plurality of integrated circuit dies that meet a predetermined standard are then identified. The programmable memory device is subsequently programmed to identify the selected integrated circuit dies.

Abstract: A bit selection and routing apparatus and method selects m data signals from among its n available data inputs and groups those m signals on its output lines. The apparatus employs a two-dimensional array of signal selection elements which are multiplexing elements. The circuitry is implemented in NMOS technology using pass transistors. The apparatus can be placed in a data flow path and can pass data either unaltered, in a selection mode, in a shift mode, and in a partial data pass mode wherein an upper portion of the input word is set to a predetermined value. The selection elements are connected to route the selected input signals to selected output lines in a predetermined order.