Abstract: The present invention retrieves data across independent computer nodes of a server cluster by providing for I/O shipping of block level requests to peer intelligent host-bus adapters (hereinafter referred to as HBA). This peer-to-peer distribution of block I/O requests is transparent to the host. The HBA has the intelligence to decide whether to satisfy a block I/O request locally or remotely. Each HBA driver utilizes the I2O protocol, which allows peer-to-peer communication independent of the operating system or hardware of the underlying network. In a first embodiment of the present invention, local and remote storage channels, within a node, are supported by a single HBA. In a second embodiment of the present invention, local storage channels, within a node, are supported by one HBA, and the remote storage channel, within a node, is supported by a separate HBA.

Abstract: Multiple subsystem I/O (Input/Output) buses are coupled to one or more system buses of a computer system by interface circuits which perform necessary decoding of memory space and I/O (Input/Output) space for allocation of portions of the memory space and the I/O (Input/Output) space to each I/O (Input/Output) bus. The interface circuits also translate fixed addresses within each I/O (Input/Output) bus to permit proper operation of the I/O (Input/Output) buses with the computer system. The interface circuits are programmed by the computer system to define the allocated memory spaces and I/O (Input/Output) spaces for the corresponding I/O (Input/Output) buses. Programming of the I/O (Input/Output) buses is performed at the time of system configuration by writing appropriate values into configuration registers incorporated into each of the interface circuits.

Abstract: In a computer system, a direct access, independently arbitrated video bus (connected to a personal computer (PC) -compatible video subsystem) is directly coupled to one or more dual-ported processors to eliminate video cycle traffic over the system bus or buses and I/O bus, thereby improving system performance. The preferred embodiment architecture has, in addition to the video bus, multiple processors coupled to at least two independently arbitrated system buses which are coupled to at least two independently arbitrated input/output (I/O) buses, to provide for rapid bus information signal transfer rates.

Abstract: A Peripheral Component Interconnect (PCI) bus for component level interconnection of processors, peripherals and memories. The PCI bus is a physical interconnect apparatus intended for use between highly integrated peripheral controller components and processor/memory systems. The PCI bus is intended as a standard interface at the component level in much the same way that ISA, EISA, or Micro Channel.TM. buses are standard interfaces at the board level. Just as ISA, EISA, and Micro Channel.TM. buses provide a common I/O board interface across different platforms and different processor generations, the PCI bus is intended to be a common I/O component interface across different platforms and different processor generations. The PCI bus lends itself to use as a main memory bus, and can be used with various cache memory techniques.

Abstract: A Peripheral Component Interconnect (PCI) bus provides component level interconnection of processors, peripherals and memories. A bus protocol mechanism includes a Special Cycle command for defining "soft", i.e., configurable, transaction types for use between devices communicating on the PCI bus. Using the Special Cycle command, two or more devices attached to the bus can establish a device-specific logical signalling channel that expands upon, but does not violate, the PCI specification. This device-specific signalling channel provides logical sideband signaling between PCI bus devices, when such signaling does not require the precise timing or synchronization of physical signals. This allows the systems designer to define necessary sideband signalling without requiring any additional pins on the PCI bus.

Abstract: A Peripheral Component Interconnect (PCI) bus has a protocol that guarantees that at all times, except for turn-around clocks necessary to prevent contention, that the bus is actively driven to a logic 1 or 0 by some device attached thereto. As long as all devices attached to the bus are compliant with the specification, the bus will never be left floating for long intervals, and thus the system designer is free to eliminate the pull-up resistors typically required on other buses.

Abstract: A cathodic protection system for a burial casket comprises a sacrificial anode rod, nylon sleeves encircling the rod and metal straps positively positioned relative the sleeves and welded to the casket bottom. One of the sleeves encircles the resistor of the system. The lead of the resistor connected between the casket and strap is carried in a slot in the one sleeve. The strap includes a welding dimple and a dog-eared corner which traps the lead between the casket bottom and the strap during welding of the strap to the bottom.

Abstract: An asynchronous transfer mode network interface is provided to multiplex isochronous and bursty data traffic over a single logical connection. Isochronous data is received by the network interface and stored in a buffer for subsequent multiplexing with bursty data received and stored in a buffer and for transmission over the single logical connection.

Abstract: A retry scheme for optimizing use of a first bus in a computer system which includes a plurality of bus masters connected through the first bus to an interface circuit and second bus. The interface circuit includes logic for generating a busy signal when the second bus is in a busy state and logic for generating a retry signal when the interface circuit is addressed by a bus master while the second bus is in a busy state. Each bus master includes logic for receiving the retry signal and relinquishing control of the common bus upon receipt of the retry signal from the interface circuit. A bus arbiter includes logic for receiving the busy signal and preventing any bus master seeking access to the second bus from participating in arbitration for control of the common first bus until the busy signal has been negated. Thus, during the term of the busy signal the first bus may be controlled by any bus master not requiring access to the shared resource.

Abstract: A dual-port processor architecture wherein a first port interfaces to a PCI bus and a second port interfaces to a RAMBUS channel.

Abstract: Multiple processor systems are configured to include at least two system or memory buses with at least two processors coupled to each of the system buses, and at least two I/O buses which are coupled to the system buses to provide multiple expansion slots hosting up to a corresponding number of I/O bus agents for the systems at the cost of a single system bus load for each I/O bus. Each of the system and I/O buses are independently arbitrated to define decoupled bus systems for the multiple processor systems of the present invention. Main memory for the systems is made up of at least two memory interleaves, each of which can be simultaneously accessed through the system buses. Each of the I/O buses are interfaced to the system buses by an I/O interface circuit which buffers data written to and read from the main memory or memory interleaves by I/O bus agents.

Abstract: System configuration, monitoring and control functions are performed in a computer system by means of a serial test bus which is incorporated into the computer system for testing components, for example integrated circuits, used to construct one or more modules of the system. The conventional serial test bus is modified to include register circuitry on modules of the computer system and/or within integrated circuits which are interconnected to construct the modules. These registers are written and read by the serial test bus for configuring the computer system as well as performing other operations such as monitoring and error logging within the computer system. To extend the amount of information which can be contained within these registers, preferably memory devices such as EEPROM, RAM, and the like, are associated with the registers and accessible therethrough.

Abstract: A buffer management scheme for optimally configuring a data buffer within a computer system which includes a plurality of bus masters connected through a Micro Channel bus and the data buffer to a shared resource, such as memory. The scheme decodes unique four-bit Micro Channel arbitration values assigned to the bus masters to retrieve buffer configuration parameters stored within a register file containing different configuration parameters for each bus master. The data buffer is dynamically configured for optimal performance with each bus master having control of the Micro Channel bus in accordance with the parameter data retrieved from the register file.

Abstract: In a processing system any response to an interrupt acknowledge cycle is deferred until the transfer of buffered data to be written from an agent on a subsystem I/O bus to main memory of the system is assured. To expedite system operation, data to be written to main memory by an agent on an I/O bus is buffered in an interface circuit. As soon as the data is buffered, the I/O bus agent is released and interrupts a processor on the system bus indicating completion of the data write. A tightly coupled interrupt controller is used so that the agent does not need to own the I/O or system bus to generate the interrupt. The interrupted processor issues an interrupt acknowledge (IAK) cycle on the system bus to receive an interrupt vector from the interrupt controller. The interface circuit recognizes the IAK cycle and generates a retry signal for the processor if buffered data remains in the interface circuit.

Abstract: A means and a method of interfacing a memory controller with a high speed synchronous CPU wherein the CPU clock is independent of the memory controller clock. The CPU clock is connected to both the CPU and a control interface state tracker located externally to the memory controller. The control interface state tracker is then connected to the memory controller. A separate clock independent from the one used with the CPU is coupled to the memory controller and drives the operation of the memory controller. During the operation of the computer system, the CPU makes read or write cycle requests of the memory controller. Such cycles are initiated when the CPU sends a cycle "start" indicator to the state tracker. In response, the state tracker activates a start strobe to the memory controller to start the actual memory cycle. The memory controller receives the CPU address and cycle status and determines the page hit/miss condition of the memory access.