Patents by Inventor Thomas F. Hummel

Thomas F. Hummel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11119929
    Abstract: Systems and methods of multi-chip processing with low latency and congestion. In a multi-chip processing system, each chip includes a plurality of clusters arranged in a mesh design. A respective interconnect controller is disposed at the end of each column. The column is linked to a corresponding remote column in the other chip. A share cache controller in the column is paired with a corresponding cache controller in the remote column, the pair of cache controllers are configured to control data caching for a same set of main memory locations. Communications between cross-chip cache controllers are performed within linked columns of clusters via the column-specific inter-chip interconnect controllers.
    Type: Grant
    Filed: January 31, 2019
    Date of Patent: September 14, 2021
    Assignee: Marvell Asia Pte, Ltd.
    Inventors: Craig Barner, David Asher, Richard Kessler, Bradley Dobbie, Daniel Dever, Thomas F. Hummel, Isam Akkawi
  • Patent number: 11036643
    Abstract: A network processor includes a memory subsystem serving a plurality of processor cores. The memory subsystem includes a hierarchy of caches. A mid-level instruction cache provides for caching instructions for multiple processor cores. Likewise, a mid-level data cache provides for caching data for multiple cores, and can optionally serve as a point of serialization of the memory subsystem. A low-level cache is partitionable into partitions that are subsets of both ways and sets, and each partition can serve an independent process and/or processor core.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: June 15, 2021
    Assignee: MARVELL ASIA PTE, LTD.
    Inventors: David H. Asher, Daniel E. Dever, Thomas F. Hummel, Shubhendu S. Mukherjee
  • Patent number: 9596193
    Abstract: In one embodiment, a system includes a packet reception unit. The packet reception unit is configured to receive a packet, create a header indicating scheduling of the packet in a plurality of cores and concatenate the header and the packet. The header is based on the content of the packet. In one embodiment, a system includes a transmit silo configured to store a multiple fragments of a packet, the fragments having been sent to a destination and the transmit silo having not received an acknowledgement of receipt of the fragments from the destination. The system further includes a restriction verifier coupled with the transmit silo. The restriction verifier is configured to receive the fragments and determine whether the fragments can be sent and stored in the transmit silo.
    Type: Grant
    Filed: December 14, 2011
    Date of Patent: March 14, 2017
    Assignee: Cavium, Inc.
    Inventors: Richard E. Kessler, Thomas F. Hummel, Robert A. Sanzone, Daniel A. Katz, Michael S. Bertone
  • Patent number: 9264385
    Abstract: In one embodiment, a system includes reassembly stores configured to store a fragment of a packet in a particular reassembly store corresponding with the packet, and when the particular reassembly store contains fragments of the packet representing the packet as a whole, forward the packet to a plurality of cores. The system further includes a packet reception unit configured to store the fragment in one of a plurality of memories within the reassembly stores, and, when the one of the plurality of memories is filled, copy the at least one fragment to a memory external to the packet reception unit.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: February 16, 2016
    Assignee: Cavium, Inc.
    Inventors: Richard E. Kessler, Thomas F. Hummel, Robert A. Sanzone, Daniel A. Katz, Michael S. Bertone
  • Patent number: 9219560
    Abstract: In one embodiment, a multiprotocol interface includes a physical layer transmitter unit configured to transmit data from synchronous media access control layer units and asynchronous media access control layer units. The multiprotocol interface also includes a physical layer receiver unit configured to receive data and to deliver the received data to the synchronous media access control layer units and the asynchronous media access control layer units. The physical layer transmitter unit and the physical layer receiver unit are both configured to operate in either an asynchronous mode or a synchronous mode. The physical layer transmitter unit and the physical layer receiver unit transmit and receive only with the asynchronous media access control units, and physical layer transmitter unit and the physical layer receiver unit transmit and receive only with the synchronous media access control units.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: December 22, 2015
    Assignee: Cavium, Inc.
    Inventor: Thomas F. Hummel
  • Publication number: 20150288625
    Abstract: In one embodiment, a system includes reassembly stores configured to store a fragment of a packet in a particular reassembly store corresponding with the packet, and when the particular reassembly store contains fragments of the packet representing the packet as a whole, forward the packet to a plurality of cores. The system further includes a packet reception unit configured to store the fragment in one of a plurality of memories within the reassembly stores, and, when the one of the plurality of memories is filled, copy the at least one fragment to a memory external to the packet reception unit.
    Type: Application
    Filed: June 22, 2015
    Publication date: October 8, 2015
    Inventors: Richard E. Kessler, Thomas F. Hummel, Robert A. Sanzone, Daniel A. Katz, Michael S. Bertone
  • Patent number: 9065781
    Abstract: In one embodiment, a system includes a packet reception unit. The packet reception unit is configured to receive a packet, create a header indicating scheduling of the packet in a plurality of cores and concatenate the header and the packet. The header is based on the content of the packet. In one embodiment, a system includes a transmit silo configured to store a multiple fragments of a packet, the fragments having been sent to a destination and the transmit silo having not received an acknowledgement of receipt of the fragments from the destination. The system further includes a restriction verifier coupled with the transmit silo. The restriction verifier is configured to receive the fragments and determine whether the fragments can be sent and stored in the transmit silo.
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: June 23, 2015
    Assignee: Cavium, Inc.
    Inventors: Richard E. Kessler, Thomas F. Hummel, Robert A. Sanzone, Daniel A. Katz, Michael S. Bertone
  • Publication number: 20140079071
    Abstract: In one embodiment, a system includes a packet reception unit. The packet reception unit is configured to receive a packet, create a header indicating scheduling of the packet in a plurality of cores and concatenate the header and the packet. The header is based on the content of the packet. In one embodiment, a system includes a transmit silo configured to store a multiple fragments of a packet, the fragments having been sent to a destination and the transmit silo having not received an acknowledgement of receipt of the fragments from the destination. The system further includes a restriction verifier coupled with the transmit silo. The restriction verifier is configured to receive the fragments and determine whether the fragments can be sent and stored in the transmit silo.
    Type: Application
    Filed: September 13, 2013
    Publication date: March 20, 2014
    Applicant: Cavium, Inc.
    Inventors: Richard E. Kessler, Thomas F. Hummel, Robert A. Sanzone, Daniel A. Katz, Michael S. Bertone
  • Patent number: 8634509
    Abstract: A high-linearity Phase Interpolator based Clock and Data Recovery (CDR) circuit for use in a multi-standard Serializer/Deserializer (SerDes) is provided. By interpolating at a high, fixed frequency for all supported data rates and then dividing the output clock down to the appropriately frequency for each standard, the Phase Interpolator can provide for maximum phase linearity while reducing its sensitivity to noise.
    Type: Grant
    Filed: February 15, 2012
    Date of Patent: January 21, 2014
    Assignee: Cavium, Inc.
    Inventors: Ethan Crain, Thomas F. Hummel, Thucydides Xanthopoulos, Scott Meninger
  • Publication number: 20130101058
    Abstract: In one embodiment, a multiprotocol interface includes a physical layer transmitter unit configured to transmit data from synchronous media access control layer units and asynchronous media access control layer units. The multiprotocol interface also includes a physical layer receiver unit configured to receive data and to deliver the received data to the synchronous media access control layer units and the asynchronous media access control layer units. The physical layer transmitter unit and the physical layer receiver unit are both configured to operate in either an asynchronous mode or a synchronous mode. The physical layer transmitter unit and the physical layer receiver unit transmit and receive only with the asynchronous media access control units, and physical layer transmitter unit and the physical layer receiver unit transmit and receive only with the synchronous media access control units.
    Type: Application
    Filed: October 25, 2011
    Publication date: April 25, 2013
    Applicant: Cavium, Inc.
    Inventor: Thomas F. Hummel
  • Publication number: 20120207259
    Abstract: A high-linearity Phase Interpolator based Clock and Data Recovery (CDR) circuit for use in a multi-standard Serializer/Deserializer (SerDes) is provided. By interpolating at a high, fixed frequency for all supported data rates and then dividing the output clock down to the appropriately frequency for each standard, the Phase Interpolator can provide for maximum phase linearity while reducing its sensitivity to noise.
    Type: Application
    Filed: February 15, 2012
    Publication date: August 16, 2012
    Applicant: Cavium, Inc.
    Inventors: Ethan Crain, Thomas F. Hummel, Thucydides Xanthopoulos, Scott Meninger
  • Publication number: 20120155474
    Abstract: In one embodiment, a system includes a packet reception unit. The packet reception unit is configured to receive a packet, create a header indicating scheduling of the packet in a plurality of cores and concatenate the header and the packet. The header is based on the content of the packet. In one embodiment, a system includes a transmit silo configured to store a multiple fragments of a packet, the fragments having been sent to a destination and the transmit silo having not received an acknowledgement of receipt of the fragments from the destination. The system further includes a restriction verifier coupled with the transmit silo. The restriction verifier is configured to receive the fragments and determine whether the fragments can be sent and stored in the transmit silo.
    Type: Application
    Filed: December 14, 2011
    Publication date: June 21, 2012
    Applicant: Cavium, Inc.
    Inventors: Richard E. Kessler, Thomas F. Hummel, Robert A. Sanzone, Daniel A. Katz, Michael S. Bertone
  • Patent number: 7895431
    Abstract: A method and apparatus for ordering, synchronizing and scheduling work in a multi-core network services processor is provided. Each piece of work is identified by a tag that indicates how the work is to be synchronized and ordered. Throughput is increased by processing work having different tags in parallel on different processor cores. Packet processing can be broken up into different phases, each phase having a different tag dependent on ordering and synchronization constraints for the phase. A tag switch operation initiated by a core switches a tag dependent on the phase. A dedicated tag switch bus minimizes latency for the tag switch operation.
    Type: Grant
    Filed: December 6, 2004
    Date of Patent: February 22, 2011
    Assignee: Cavium Networks, Inc.
    Inventors: Gregg A. Bouchard, Thomas F. Hummel, Richard E. Kessler, Muhammed R. Hussain, Yen Lee
  • Patent number: 7535907
    Abstract: A network transport layer accelerator accelerates processing of packets so that packets can be forwarded at wire-speed. To accelerate processing of packets, the accelerator performs pre-processing on a network transport layer header encapsulated in a packet for a connection and performs in-line network transport layer checksum insertion prior to transmitting a packet. A timer unit in the accelerator schedules processing of the received packets. The accelerator also includes a free pool allocator which manages buffers for storing the received packets and a packet order unit which synchronizes processing of received packets for a same connection.
    Type: Grant
    Filed: September 2, 2005
    Date of Patent: May 19, 2009
    Assignee: Oavium Networks, Inc.
    Inventors: Muhammad R. Hussain, Imran Badr, Faisal Masood, Philip H. Dickinson, Richard E. Kessler, Daniel A. Katz, Michael S. Bertone, Robert A. Sanzone, Thomas F. Hummel, Gregg A. Bouchard