Patents by Inventor Thomas F. Joyce

Thomas F. Joyce has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10840590
    Abstract: An antenna assembly has a main body configured to receive an antenna, and an uninterrupted top cap attached to the main body. The uninterrupted top cap has an outer surface. A lifting assembly is attached to at the outer surface of said top cap without penetrating the cap. Accordingly, the uninterrupted cap forms an unbroken whole. The uninterrupted cap is continuous without any through-holes or other perturbances or features that extend through the cap or otherwise might allow fluid to pass through the cap into an interior of the main body.
    Type: Grant
    Filed: April 17, 2020
    Date of Patent: November 17, 2020
    Assignee: Amphenol Antenna Solutions, Inc.
    Inventors: Griffin M. Wolf, Charles E. Gaither, Thomas F. Aberasturi, Aaron M. Joyce
  • Patent number: 6311286
    Abstract: The invention is directed to a memory controller for use with memory having varying timing characteristics. In particular, the timing characteristics of the various memory devices are determined and used to generate timing signals commensurate with each particular memory device.
    Type: Grant
    Filed: June 10, 1994
    Date of Patent: October 30, 2001
    Assignee: NEC Corporation
    Inventors: James F. Bertone, Bruno DiPlacido, Jr., Thomas F Joyce, Martin Massucci, Lance J. McNally, Thomas L. Murray, Jr., Chester M. Nibby, Jr., Michelle A. Pence, Marc Sanfacon, Jian-Kuo Shen, Jeffrey S. Somers, G. Lewis Steiner
  • Patent number: 6125436
    Abstract: A symmetric multiprocessing system with a unified environment and distributed system functions provides unified address space for all functional units in the system while distributing the execution of various system functions over the functional units of the system whereby each functional unit assumes responsibility for its own aspects of these operations. In addition, the system provides improved system bus operation for transfer of data from memory.
    Type: Grant
    Filed: May 12, 1997
    Date of Patent: September 26, 2000
    Assignee: NEC Corporation
    Inventors: James F. Bertone, Bruno DiPlacido, Jr., Thomas F. Joyce, Martin Massucci, Lance J. McNally, Thomas L. Murray, Jr., Chester M. Nibby, Jr., Michelle A. Pence, Marc Sanfacon, Jian-Kuo Shen, Jeffrey S. Somers, G. Lewis Steiner
  • Patent number: 5956522
    Abstract: A symmetric multiprocessing system with a unified environment and distributed system functions provides unified address space for all functional units in the system while distributing the execution of various system functions over the functional units of the system whereby each functional unit assumes responsibility for its own aspects of these operations. In addition, the system provides improved system bus operation for transfer of data from memory.
    Type: Grant
    Filed: March 16, 1995
    Date of Patent: September 21, 1999
    Assignee: Packard Bell NEC
    Inventors: James F. Bertone, Bruno DiPlacido, Jr., Thomas F Joyce, Martin Massucci, Lance T. McNally, Thomas L. Murray, Jr., Chester M. Nibby, Jr., Michelle A. Pence, Marc Sanfacon, Jian-Kuo Shen, Jeffrey S. Somers, G. Lewis Steiner
  • Patent number: 5809340
    Abstract: Timing calculator means in a computer system are used to adaptively generate an appropriate access signal, to one of a plurality of memory types, based on first and second timing control values, wherein the first timing control value represents information specific to and limited to the start of a memory operation and wherein the second timing control value represents information representing other timing events. That is, the state machine of the present invention requires a distinct starting control value, separate from other timing values, for calculation of appropriate memory access parameters.
    Type: Grant
    Filed: August 12, 1997
    Date of Patent: September 15, 1998
    Assignee: Packard Bell NEC
    Inventors: James F. Bertone, Bruno DiPlacido, Jr., Thomas F. Joyce, Martin Massucci, Lance J. McNally, Thomas L. Murray, Jr., Chester M. Nibby, Jr., Michelle A. Pence, Marc Sanfacon, Jian-Kuo Shen, Jeffrey S. Somers, G. Lewis Steiner, William S. Wu, Norman J. Rasmussen, Suresh K. Marisetty, Puthiya K. Nizar
  • Patent number: 5522069
    Abstract: A symmetric multiprocessing system with a unified environment and distributed system functions provides unified address space for all functional units in the system while distributing the execution of various system functions over the functional units of the system whereby each functional unit assumes responsibility for its own aspects of these operations. In addition, the system provides improved system bus operation for transfer of data from memory.
    Type: Grant
    Filed: June 10, 1994
    Date of Patent: May 28, 1996
    Assignee: Zenith Data Systems Corporation
    Inventors: James F. Bertone, Bruno DiPlacido, Jr., Thomas F. Joyce, Martin Massucci, Lance J. McNally, Thomas L. Murray, Jr., Chester M. Nibby, Jr., Michelle A. Pence, Marc Sanfacon, Jian-Kuo Shen, Jeffrey S. Somers, G. Lewis Steiner, William S. Wu, Norman J. Rasmussen, Suresh K. Marisetty, Puthiya K. Nizar
  • Patent number: 5517648
    Abstract: A symmetric multiprocessing system with a unified environment and distributed system functions provides unified address space for all functional units in the system while distributing the execution of various system functions over the functional units of the system whereby each functional unit assumes responsibility for its own aspects of these operations. In addition, the system provides improved system bus operation for transfer of data from memory.
    Type: Grant
    Filed: March 16, 1995
    Date of Patent: May 14, 1996
    Assignee: Zenith Data Systems Corporation
    Inventors: James F. Bertone, Bruno DiPlacido, Jr., Thomas F. Joyce, Martin Massucci, Lance J. McNally, Thomas L. Murray, Jr., Chester M. Nibby, Jr., Michelle A. Pence, Marc Sanfacon, Jian-Kuo Shen, Jeffrey S. Somers, G. Lewis Steiner
  • Patent number: 5430862
    Abstract: The emulator includes first and second pipelined stages connected through a bidirectional bus for executing source instructions normally executed by a different/source computer in a highly overlapped manner. The first stage includes an emulator chip which performs the function of fetching and decoding each source instruction stored in cache memory resulting in the generation of a number of vector addresses required for executing the instruction by the second stage. The second stage includes a high performance microprocessor chip having on-chip instruction and data caches for storing a plurality of emulation subroutines and data fetched during subroutine execution. In pipelined fashion, the emulator chip fetches and decodes each source instruction which generates a vector branch address which is loaded into the branch vector register while the microprocessor chip fetches and executes emulation subroutines specified by the vector address transferred via the bus for each previously decoded source instruction.
    Type: Grant
    Filed: June 29, 1990
    Date of Patent: July 4, 1995
    Assignee: Bull HN Information Systems Inc.
    Inventors: Steven S. Smith, Arnold J. Smith, Amy E. Gilfeather, Richard P. Brown, Thomas F. Joyce
  • Patent number: 5341508
    Abstract: A processing unit tightly couples to a system bus and includes a local memory which is accessible from such bus. The processing unit includes a high performance microprocessor which tightly couples to the local memory through a high speed synchronous bus shared with a plurality of synchronous state machines. A microprocessor internal bus state machine and the plurality of state machines control local bus accesses for transferring commands generated by the microprocessor and commands transferred from the system bus under the control of an external state machine for execution by a local memory state machine and the processor state machine, respectively, which also couples to the system bus.
    Type: Grant
    Filed: October 4, 1991
    Date of Patent: August 23, 1994
    Assignee: Bull HN Information Systems Inc.
    Inventors: James W. Keeley, Thomas F. Joyce
  • Patent number: 5341495
    Abstract: A processing unit tightly couples to a system bus which utilizes a split cycle bus protocol and includes a local memory which is accessible from such bus. The local memory couples to a high speed synchronous bus which operates according to a predetermined bus protocol. The processing unit includes a state machine which couples to the high speed synchronous bus and to the asynchronous system bus. The state machine emulates the predetermined bus synchronous protocol in transferring commands issued to the local memory from the system bus which uses the split cycle protocol.
    Type: Grant
    Filed: October 4, 1991
    Date of Patent: August 23, 1994
    Assignee: Bull HN Information Systems, Inc.
    Inventors: Thomas F. Joyce, James W. Keeley, Richard A. Lemay, Bruno DiPlacido, Jr., Martin M. Massucci
  • Patent number: 5287522
    Abstract: A system includes first and second processing units which are interconnected by a bidirectional bus. The first processing unit is a microprocessor chip programmed for executing procedures stored in an on-chip instruction cache unit. The second processing unit receives requests from an external source such as a system bus. The microprocessor chip includes a branch vector facility which connects to the bus. The second processing unit in response to an external request, generates a vector branch address. The processing unit transfers the vector branch address to the branch vector facility for storage along with setting a write indicator. The microprocessor chip, upon detecting that the write indicator was set, branches to the procedure specified by the branch vector address for executing the instructions of the procedure to carry out those operations required for processing the external request or event.
    Type: Grant
    Filed: June 29, 1990
    Date of Patent: February 15, 1994
    Assignee: Bull HN Information Systems, Inc.
    Inventors: Richard P. Brown, Thomas F. Joyce, Steven S. Smith
  • Patent number: 5283870
    Abstract: A multiprocessor system includes a number of system processors which tightly couple to a system bus to share a main or system memory and a number of on-board memory processors which also are tightly coupled to the system bus. Each processor has a high performance microprocessor which tightly couples to an on-board or local memory through the microprocessor's local bus. System memory is accessible using a memory lock protocol while the local memory is accessible through a bus lock protocol. Each on-board memory processor includes a lock mechanism which enables the processing of memory lock commands directed to its local memory received via the system bus from any other processor and for issuing memory lock commands to system memory.
    Type: Grant
    Filed: October 4, 1991
    Date of Patent: February 1, 1994
    Assignee: Bull HN Information Systems Inc.
    Inventors: Thomas F. Joyce, James W. Keeley
  • Patent number: 5193181
    Abstract: The pipelined central processing system (CSS) units of a multiprocessor system are tightly coupled to connect in common to a system bus for sharing main memory and input/output controllers/devices. The CSS includes several circuit boards for the different VLSI circuit chip pipelined stages and associated control circuits in addition to the bus interface unit (BIU) circuits. Each board includes one or more unusual event (UEV) detector circuits for signaling when the behavior of a stage is abnormal. The UEV fault signals from each board are collected by the BIU board. When a UEV fault is detected, the BIU board circuits prevent any further communications with the system bus and broadcasts the UEV fault signal to the other boards causing the different pipelined stages to emulate the completion of the instructions within the pipeline thereby flushing it. It is thereafter placed in a nonpipelined mode.
    Type: Grant
    Filed: October 5, 1990
    Date of Patent: March 9, 1993
    Assignee: Bull HN Information Systems Inc.
    Inventors: George J. Barlow, James W. Keeley, Richard A. Lemay, Jian-Kuo Shen, Robert V. Ledoux, deceased, Thomas F. Joyce, Richard P. Kelly, Robert C. Miller
  • Patent number: 5148533
    Abstract: In a data processing system having a plurality of tightly coupled data processing units connected by an asynchronous system bus, apparatus and an associated method are described for maintaining the coherency of data groups stored in instruction cache units and execution cache units. The apparatus includes a monitor unit as part of the bus interface unit, and a bus interface unit coupling each associated data processing unit to the system bus. The monitor unit receives signals, applied to the system bus, identifying data groups transferred between the memory unit and the data processing units, including those data groups originating from the bus interface unit of which the monitor unit is a component. The bus interface unit includes directories duplicating the contents of the instruction cache unit directory and the execution cache unit directory.
    Type: Grant
    Filed: January 5, 1989
    Date of Patent: September 15, 1992
    Assignee: Bull HN Information Systems Inc.
    Inventors: Thomas F. Joyce, Robert C. Miller, Marc C. Vogt
  • Patent number: 5148530
    Abstract: In a data processing system using a virtual memory adressing scheme, certain software instructions call for the virtual address to be stored in a base register. The virtual address stored in the base register is incremented or decremented during the read out cycle of the previous operand to address the next operand. If the operand is not in physical memory, then the contents of the base register is restored to its original value.
    Type: Grant
    Filed: September 6, 1989
    Date of Patent: September 15, 1992
    Assignee: Bull HN Information Systems Inc.
    Inventors: Thomas F. Joyce, Richard P. Kelly, Jian-Kuo Shen
  • Patent number: 5123097
    Abstract: In a data processing system in which each of the data processing units is implemented using pipeline techniques and has a cache memory unit employing a store through strategy, the time required to prepare a write instruction operand address can be substantially shorter than the time required by the execution unit to prepare the associated write instruction operand. In order to utilize the time difference, apparatus is included in the execution cache unit for storing the write instruction operand address during the preparation of the associated write instruction operand. After storing the write instruction operand address, a next address is entered in an input register of the execution cache unit. When the newly entered address is associated with a read instruction, does not conflict with the write instruction operand address, and produces a "hit" signal when applied to the execution cache unit tag directory, the read instruction is processed by the execution unit.
    Type: Grant
    Filed: January 5, 1989
    Date of Patent: June 16, 1992
    Assignee: Bull HN Information Systems Inc.
    Inventors: Thomas F. Joyce, Ming T. Miu, Richard P. Kelly
  • Patent number: 5053951
    Abstract: A segment descriptor unit (SDU) includes a divided random access memory (RAM), a content addressable memory (CAM) and decoder circuits interconnected for performing dynamic and static address translation operations within a minimum of chip area and power. The CAM is arranged to store a number of entries which include segment number and validity information associated with a corresponding number of segment descriptors. The RAM contains locations allocated for storing segment descriptor words (SDW's) and working data. Each SDW is logically divided into two fields, a static translation word (STW) field containing all of the bits required for performing a static address translation operation and an access control word (ACW) field containing all of the bits required for verifying compliance with system security. The bits of each STW and ACW are stored in alternate bit positions of the SDW locations. Each pair of RAM bit locations couple to a common read/write amplifier and multiplexer circuit.
    Type: Grant
    Filed: March 28, 1989
    Date of Patent: October 1, 1991
    Assignee: Bull HN Information Systems Inc.
    Inventors: Eugene Nusinov, Thomas F. Joyce
  • Patent number: 5051894
    Abstract: In a data processing system in which the execution unit is implemented to process aligned double word operands, apparatus and an associated method provide for the alingment of a double word operand that is stored across a double work boundary. The two double words each storing a word of the unaligned double word operand are identified and the attributes are compared with the ring number of the associated program. When the comparisons indicate that the two words of the non-aligned double word operand are available to the program, the two double word operands containing the non-aligned words of the double word operand, and the two non-aligned words are stored in a register in an aligned orientation for processing by the execution unit.
    Type: Grant
    Filed: January 5, 1989
    Date of Patent: September 24, 1991
    Assignee: Bull HN Information Systems Inc.
    Inventors: Forrest M. Phillips, Thomas F. Joyce, Ming T. Miu
  • Patent number: 4942547
    Abstract: A data processing system includes the functionality of a commercial instruction processor, a scientific instruction processor and a basic instruction processor integrated into a single semiconductor logic element.
    Type: Grant
    Filed: December 7, 1987
    Date of Patent: July 17, 1990
    Assignee: Honeywell Bull, Inc.
    Inventors: Thomas F. Joyce, Richard P. Kelly, Jian-Kuo Shen, Michel M. Raguin
  • Patent number: 4901222
    Abstract: In a data processing system using a virtual memory addressing scheme, certain software instructions call for the virtual address to be stored in a base register. The virtual address stored in the base register is incremented or decremented during the read out cycle of the previous operand to address the next operand. If the operand is not in physical memory, then the contents of the base register is restored to its original value. This invention minimizes the amount of logic required to back out of a software instruction after execution has begun and is faster than checking if all resources are present before any state change is made during the execution of a software instruction.
    Type: Grant
    Filed: May 19, 1987
    Date of Patent: February 13, 1990
    Assignee: Bull NH Information Systems Inc.
    Inventors: Thomas F. Joyce, Richard P. Kelly, Jian-Kuo Shen