Abstract: A programmable integrated circuit utilizes a large number of intermediate-grain processing elements which are multibit processing units arranged in a configurable mesh. The coarse-grain resources, such as memory and processing, are deployable in a way that takes advantage of the opportunities for optimization present in given problems. To accomplish this, the interconnect supports three different modes of operation: a static value in which a value set by the configuration data is provided to a functional unit, static source in which another functional unit serves as the value source, and a dynamic source mode in which the source is determined by the value from another functional unit.

Abstract: The present invention provides a visual display including a high resolution miniature display compatible with VLSI technology and an optical system such as an optical magnifier used to enlarge the images display on the miniature display to be visible to the naked eye. The miniature display includes a VLSI backplane having an array of display elements monolithically formed with its driving circuit on a single crystalline semiconductor. Signal processing circuit or a microprocessor used to process image signals for the display may also be formed monolithically with the array and its driving circuit. The array may be designed using a silicon software compiler program to have randomly displaced elements or super-pixels for reducing image aliasing. The array may also be designed to have display elements positioned and scaled to compensate for the optical distortion introduced by the magnifier.

Abstract: A single chip microprocessor or memory device has reprogrammable characteristics according to the invention. In the case of the microprocessor, a fixed processing cell is provided as is common to perform logic calculations. A portion of the chip silicon real-estate, however, is dedicated a programmable gate array. This feature enables application-specific configurations to allow adaptation to the particular time-changing demands of the microprocessor and provide the functionality required to best serve those demands. This yields application acceleration and in system-specific functions. In other cases the configurable logic acts as network interface, which allows the same basic processor design to function in any environment to which the interface can adapt.The invention also concerns a memory device having a plurality of memory banks and configurable logic units associated with the memory banks. An interconnect is provided to enable communication between the configurable logic units.

Abstract: A programmable integrated circuit utilizes a large number of intermediate-grain processing elements which are multibit processing units arranged in a configurable mesh. The coarse-grain resources, such as memory and processing, are deployable in a way that takes advantage of the opportunities for optimization present in given problems. To accomplish this, the interconnect supports three different modes of operation: a static value in which a value set by the configuration data is provided to a functional unit, static source in which another functional unit serves as the value source, and a dynamic source mode in which the source is determined by the value from another functional unit.

Abstract: The present invention provides a visual display including a high resolution miniature display compatible with VLSI technology and an optical system such as an optical magnifier used to enlarge the images display on the miniature display to be visible to the naked eye. The miniature display includes a VLSI backplane having an array of display elements monolithically formed with its driving circuit on a single crystalline semiconductor. Signal processing circuit or a microprocessor used to process image signals for the display may also be formed monolithically with the array and its driving circuit. The array may be designed using a silicon software compiler program to have randomly displaced elements or super-pixels for reducing image aliasing. The array may also be designed to have display elements positioned and scaled to compensate for the optical distortion introduced by the magnifier.

Abstract: A gas transfer system is provided for establishing or maintaining a predetermined gas pressure within a plenum, such as a tire. In an exemplary embodiment, the gas transfer system includes a power source, a pressure sensor, a control unit, and a gas transfer mechanism. Preferably, a gas transfer mechanism includes a micromechanical device, comprising one or more pumping units that transfer gas from one pressure zone to another. In one embodiment, pumping is accomplished, in part, by heating the gas within a sealable chamber of a pumping unit to cause the pressure of the gas to increase. In another embodiment, the change in pressure of the gas caused by compression of a tire provides a pumping force. Valves are provided for regulating movement of the gas through the gas transfer mechanism and can include electromechanical valves responsive to signals from the control unit, or passively biased valves responsive to applied gas pressure.

Abstract: An integrated dynamically programmable gate array comprises a two dimensional array of programmable gates. These gates can be implemented as look up tables but hardwired gates with programmable interconnections are also possible. Each one of the gates receives plural input logic signals from plural other gates. Consequently, a broad range of logic combinations are possible. The gates further include locally stored multiple contexts dictating different combinatorial logic operations performed by the gates. The contexts increase the logic operations performable by the gate and the fact that the contexts are locally stored enables better integration and speed. Only a context instruction needs to be distributed among programmable gates. A context signal generator is included that generates a context signal indicating a change in an active one of the contexts. This active context dictates the logic operations of the gates that commonly receive by the signal.

Abstract: A computer implemented method for simulating a physical process. The method includes storing in a memory a state vector for each of a number of voxels. Each state vector includes a plurality of integers, each of which corresponds to a particular momentum state of a number of possible momentum states at a voxel and represents the number of elements having the particular momentum state. Each integer has more than two possible values. The method also includes performing interaction operations on the state vectors that model interactions between elements of different momentum states, performing viscosity modification operations on the state vectors to change the viscosity of the simulated physical process, and performing move operations on the state vectors that reflect movement of elements to new voxels.

Abstract: A resistor circuit includes a resistance control circuit and at least one insulated gate field effect transistor. The resistance control circuit includes a control signal output element including a reference transistor for generating a resistance control signal in response to an internal control signal to maintain the reference transistor at a selected resistance value and a resistance value control element including a reference resistor for generating a circuit control signal for controlling the resistance value of the reference transistor in relation to the resistance value provided by the reference resistor. The field effect transistor is controlled by the resistance control signal to provide a resistance value which is a function of the resistance value of the reference transistor (and therefore of the reference resistor) and ratios of selected physical characteristics of the reference transistor.

Abstract: A class of switching networks is comprised of expansive logical clusters and/or dispersive logical clusters. These clusters are of low degree. The class of networks include multibutterfly networks as well as multi-Benes networks. These networks provide for fault tolerance and routing and for efficient routing. Moreover, routing is provided in a non-blocking fashion.

Abstract: A gas transfer system is provided for establishing or maintaining a predetermined gas pressure within a plenum, such as a tire. In an exemplary embodiment, the gas transfer system includes a power source, a pressure sensor, a control unit, and a gas transfer mechanism. Preferably, a gas transfer mechanism includes a micromechanical device, comprising one or more pumping units that transfer gas from one pressure zone to another. In one embodiment, pumping is accomplished, in part, by heating the gas within a sealable chamber of a pumping unit to cause the pressure of the gas to increase. In another embodiment, the change in pressure of the gas caused by compression of a tire provides a pumping force. Valves are provided for regulating movement of the gas through the gas transfer mechanism and can include electromechanical valves responsive to signals from the control unit, or passively biased valves responsive to applied gas pressure.

Abstract: In a pipelined logic circuit, switches are only enabled when voltage differentials across the switches are zero. The switches are configured during a restored state of voltage rails, and a swing in voltage on the rails results in a swing in output voltage to a set level. To restore the logic circuit with minimal energy dissipation and permit useful pipelining, the inputs are regenerated through an inverse logic circuit. The voltage rail then swings back to its restored level. Full forward and reverse pipelines are formed with the individual forward and inverse logic circuits with the pipelines being driven by multiphase clock rails. Each logic stage includes a logic gate and a pass gate.

Abstract: A parallel processing system is receptive of a program and has at least two processors connected in parallel to a shared main memory. Each processor executes instructions of the program which includes side-effecting instructions which modify the contents of a location in main memory and functional instructions which reference locations in main memory. The program is compiled into a series of independent instruction blocks each of which includes predominantly functional instructions and terminates in a side-effecting instruction and the processors execute the blocks in parallel.

Abstract: A parallel processing circuit is disclosed for use as the processor/memory in a highly parallel processor. The circuit comprises an instruction decoder that generates tables of outputs in response to instructions received at the decoder and a plurality of processor/memories each of which comprises a read/write memory and a processor for producing an output depending at least in part on data read from the memory and instruction information received at the instruction decoder. In addition, the circuit provides means for simultaneously addressing at least one cell in each read/write memory to write data thereto or read data therefrom and means for providing to each processor an output table from the decoder, the particular output table depending on instruction information received at the decoder. Further the processing circuit comprises means for selecting from the output table a particular output depending on data input to the processor.