Abstract: An integrated circuit comprises a plurality of clock domains (10, 12). Test data is shifted into the integrated circuit through a scan chain (100, 14, 104). In a test mode a connection is interrupted between a functional output of a first clock domain (10) and a functional input of a second clock domain (12). Test data is applied from the scan chain (100, 14, 104) to the functional input and a test response is captured into from the functional output. A delay circuit (24, 28) is used to delay transfer of the test result from the scan cell (21) to the functional input when the test result is captured in the scan cell (21), to ensure that timing differences between the clock domains do not affect the test. Subsequently the test result is shifted through the scan chain.

Abstract: An integrated circuit comprises a plurality of clock domains (10, 12). Test data is shifted into the integrated circuit through a scan chain (100, 14, 104). In a test mode a connection is interrupted between a functional output of a first clock domain (10) and a functional input of a second clock domain (12). Test data is applied from the scan chain (100, 14, 104) to the functional input and a test response is captured into from the functional output. A delay circuit (24, 28) is used to delay transfer of the test result from the scan cell (21) to the functional input when the test result is captured in the scan cell (21), to ensure that timing differences between the clock domains do not affect the test. Subsequently the test result is shifted through the scan chain.

Abstract: According to an example embodiment of the present invention, there is a test access architecture for testing modules in an electronic circuit. The test access architecture includes a test access mechanism (TAM) having a plurality of modules connected in series thereto; the test access mechanism is arranged to transport test stimulus data to, and test response data from a module being tested. A global enable signal is provided for placing the modules in a test mode. A control circuit is provided between the global enable signal and an associated module; wherein the control circuit is arranged to control whether or not the global enable signal is passed to its associated module.