Abstract: Methods and systems of verifying a hardware design for a sorter are disclosed. The methods include generating a modified version of the hardware design of the sorter accepting extended inputs and performing formal verification comprising: implementing a constraint that the least significant bits of each input in a set of extended inputs represent a unique value; and formally verifying aspects of the modified version of the hardware design of the sorter for the set of extended inputs.

Abstract: A method of performing dot product of an array of ‘2k’ floating point numbers comprising two sets of k floating-point numbers ai and bi is disclosed. The method includes receiving both sets of ‘k’ floating point numbers and multiplying each floating point number ai with a floating point number bi to generate k product numbers (zi), each product number (zi) having a mantissa bit length of ‘r+log (k?1)+1’ bits. The method further comprises creating a set of ‘k’ numbers (yi) based on the k product numbers (zi), the numbers (yi) having a bit-length of ‘n’ bits. Further the method includes identifying a maximum exponent sum (emax) among k exponent sums (eabi) of each pair of floating point numbers ai and bi aligning the magnitude bits of the numbers (yi) based on the maximum exponent sum (emax) and adding the set of ‘k’ numbers concurrently to obtain the dot product.

Abstract: A method of performing dot product of an array of ‘2k’ floating point numbers comprising two sets of k floating-point numbers ai and bi is disclosed. The method includes receiving both sets of ‘k’ floating point numbers and multiplying each floating point number ai with a floating point number bi to generate k product numbers (zi), each product number (zi) having a mantissa bit length of ‘r’ bits. The method further comprises creating a set of ‘k’ numbers (yi) based on the k product numbers (zi), the numbers (yi) having a bit-length of ‘n’ bits. Further the method includes identifying a maximum exponent sum (emax) among k exponent sums (eabi) of each pair of floating point numbers ai and bi, aligning the magnitude bits of the numbers (yi) based on the maximum exponent sum (emax) and adding the set of ‘k’ numbers concurrently to obtain the dot product.

Abstract: Methods and systems of verifying a hardware design for a sorter are disclosed. The methods include generating a modified version of the hardware design of the sorter accepting extended inputs and performing formal verification comprising: implementing a constraint that the least significant bits of each input in a set of extended inputs represent a unique value; and formally verifying aspects of the modified version of the hardware design of the sorter for the set of extended inputs.

Abstract: A method and system for processing a set of ‘k’ floating point numbers to perform addition and/or subtraction is disclosed. Each floating-point number comprises a mantissa (mi) and an exponent (ei). The method comprises receiving the set of ‘k’ floating point numbers in a first format, each floating-point number in the first format comprising a mantissa (mi) with a bit-length of ‘b’ bits. The method further comprises creating a set of ‘k’ numbers (yi) based on the mantissas of the ‘k’ floating-point numbers, the numbers having a bit-length of ‘n’ bits obtained by adding both extra most-significant bits and extra least-significant bits to the bit length ‘b’ of the mantissa (mi). The method includes identifying a maximum exponent (emax) among the exponents ei, aligning the magnitude bits of the numbers (yi) based on the maximum exponent (emax) and processing the set of ‘k’ numbers concurrently.

Abstract: Methods and systems of verifying a hardware design for a sorter are disclosed. The methods include generating a modified version of the hardware design of the sorter accepting extended inputs and performing formal verification comprising: implementing a constraint that the least significant bits of each input in a set of extended inputs represent a unique value; and formally verifying aspects of the modified version of the hardware design of the sorter for the set of extended inputs.