Abstract: Implementation and specification of synchronous sequential circuits and other data-processing systems can be modeled by finite state machines. The verification, that is to say the comparison between the implementation and the specification of such systems can then be reduced to the comparison between two finite state machines. On the basis of a symbolic representation of finite state machines with the aid of binary decision diagrams, a method for comparing finite state machines has been developed which can be automatically run on computer systems and thus provides the possibility of automatically verifying such circuits without simulation.