Abstract: An electroacoustic filter has improved low-pass characteristics. The filter includes a first electroacoustic converter, an electroacoustic element and a grid structure between the converter and the element. The grid structure is acoustically active in one frequency range that lies above the acoustically active frequency range of the first electroacoustic converter.

Abstract: An electroacoustic filter has improved low-pass characteristics. The filter includes a first electroacoustic converter, an electroacoustic element and a grid structure between the converter and the element. The grid structure is acoustically active in one frequency range that lies above the acoustically active frequency range of the first electroacoustic converter.

Abstract: The present invention provides an apparatus for testing a device (102) for storing data, which has a device for comparing actual data with set point data for individual storage areas and a device for supplying a comparison signal (106) for each storage area, which comparison signal (106) has a first state if the actual data is identical to the set point data, and a second state if the actual data is not identical to the set point data. The testing apparatus has a circuit board (100) on which the storage device (102) can be mounted, and a device (108) for comparing the states of the comparison signals at the pins of the storage device (102) which are assigned to the comparison signals (106), and for supplying a status signal (110) which, as a function of the state of the comparison signal, has a first state if the storage device (102) is operationally capable, and has a second state if the storage device (102) is defective.

Abstract: The invention provides a method for testing a memory unit (113) to be tested in a test device (100), the memory unit (113) to be tested being introduced into the test device (100), a first data register (102a–102N) to be tested being read out from the memory unit (113) to be tested and being tested in a comparator unit (106), and then at least one further data register (102a–102N) to be tested being read out of the memory unit (113) to be tested and tested in a comparator unit (106).

Abstract: The invention creates a method for testing circuit units (100) to be tested, in which test output signals (107a-107n) can be combined, where test input signals (106a-106n) are input from a test device (105) into the circuit unit (100) to be tested via a connecting unit (104), the circuit unit (100) to be tested is tested by means of the test input signals (106a-106n) in order to obtain corresponding test output signals (107a-107n) which indicate an operability of the circuit unit (100) to be tested, a gate unit (101) is connected to the connecting unit (104) by means of a first test mode switching unit (102) and of a second test mode switching unit (103), in such a manner that the test output signals (107a-107n), after being logically combined in the gate unit (101), are provided as a combined test output signal (109) via a single output line (110), and the combined test output signal (109) is output to the test device (105).

Abstract: The invention provides a test arrangement for testing circuit units under test (101, 101a-101n) having a test apparatus for holding the circuit units under test (101, 101a-101n), input/output channels (DQ0-DQn) for connecting the circuit units under test (101, 101a-101n) to the test apparatus and for data interchange, and test mode output channels (103, 103a-103n) for outputting a test result signal (104, 104a-104n), where at least one diversion unit (102, 102a-102n) for connecting one of the test mode output channels (103, 103a-103n) to one of the input/output channels (DQ0-DQn) is provided in the circuit units under test (101, 101a-101n) so that the test result signal (104, 104a-104n) which is output from the circuit unit under test (101, 101a-101n) can be diverted from the circuit unit under test (101, 101a-101n) to a prescribable one of the input/output channels (DQ0-DQn).

Abstract: The invention creates a method for testing circuit units (100) to be tested, in which test output signals (107a-107n) can be combined, where test input signals (106a-106n) are input from a test device (105) into the circuit unit (100) to be tested via a connecting unit (104), the circuit unit (100) to be tested is tested by means of the test input signals (106a-106n) in order to obtain corresponding test output signals (107a-107n) which indicate an operability of the circuit unit (100) to be tested, a gate unit (101) is connected to the connecting unit (104) by means of a first test mode switching unit (102) and of a second test mode switching unit (103), in such a manner that the test output signals (107a-107n), after being logically combined in the gate unit (101), are provided as a combined test output signal (109) via a single output line (110), and the combined test output signal (109) is output to the test device (105).

Abstract: The invention provides a method for testing a memory unit (113) to be tested in a test device (100), the memory unit (113) to be tested being introduced into the test device (100), a first data register (102a-102N) to be tested being read out from the memory unit (113) to be tested and being tested in a comparator unit (106), and then at least one further data register (102a-102N) to be tested being read out of the memory unit (113) to be tested and tested in a comparator unit (106).

Abstract: The present invention provides an apparatus for testing a device (102) for storing data, which has a device for comparing actual data with set point data for individual storage areas and a device for supplying a comparison signal (106) for each storage area, which comparison signal (106) has a first state if the actual data is identical to the set point data, and a second state if the actual data is not identical to the set point data. The testing apparatus has a circuit board (100) on which the storage device (102) can be mounted, and a device (108) for comparing the states of the comparison signals at the pins of the storage device (102) which are assigned to the comparison signals (106), and for supplying a status signal (110) which, as a function of the state of the comparison signal, has a first state if the storage device (102) is operationally capable, and has a second state if the storage device (102) is defective.