Patents by Inventor Thomas Fletcher

Thomas Fletcher has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240376294
    Abstract: A composition comprising a conjugated polymer and thermally conductive flakes. A thermally conductive film may be formed from the composition. The film may be used in an electronic device, for example as an underfill.
    Type: Application
    Filed: March 30, 2022
    Publication date: November 14, 2024
    Applicant: Sumitomo Chemical Co., Ltd.
    Inventors: Thomas Fletcher, Simon King
  • Publication number: 20240076435
    Abstract: A polymer comprising a repeating structure of formula (I) wherein Ar in each occurrence is an arylene or heteroarylene group; p is at least 2; one of Y1 and Y2 is CR1 wherein R1 is H or a substituent; and the other of Y1 and Y2 is N. The polymer may be formed by reaction of monomers containing reactive groups which react to form an imine. The polymer may be used as a thermally conductive polymer, e.g. a thermally conductive layer of an electronic device.
    Type: Application
    Filed: December 22, 2021
    Publication date: March 7, 2024
    Inventors: Simon Mark King, Przemyslaw Gawel, Thomas Fletcher
  • Publication number: 20230416601
    Abstract: A chiral polymer comprising a repeat unit having a first planar group disposed in a first plane; a second planar group disposed in a second plane different from the first plane; a bond or group linking the first planar group and the second planar group; and a first divalent binding group linking the first planar group and the second planar group. The polymer may be used as the active material of an electrooptic modulator.
    Type: Application
    Filed: October 29, 2021
    Publication date: December 28, 2023
    Inventors: Matthew Roberts, Przemek Gawel, Philip Benze, Jon Pillow, Michael Cass, Simon King, Martin Humphries, Thomas Fletcher
  • Publication number: 20230268309
    Abstract: An electrically non-conducting film (109) comprising an oligomer comprising an arylene or heteroarylene repeating unit is disposed between a chip (105), e.g. a flip-chip, and a functional layer (101), e.g. a printed circuit board, electrically connected to the chip by electrically conducting interconnects (107). The oligomer may be crosslinked.
    Type: Application
    Filed: July 2, 2021
    Publication date: August 24, 2023
    Inventors: Martin Humphries, Simon King, Thomas Fletcher, Antonio Attanzio, Kiran Kamtekar
  • Patent number: 11344116
    Abstract: A furniture system is provided having a support to be mounted to an upright structure of a building, and a shelf that is assembled onto the support. The shelf has a load-bearing surface, a front side, and a rear side with a first connector. The support has an outer face that includes at least one second connector. The first and second connectors are configured to interconnect such that, in the assembled the furniture system, the shelf is supported by the support with the load bearing surface projecting horizontally away from the upright structure, the first and second connectors resist rotation of the shelf about the first and second connectors by a force acting downwardly through the load bearing surface, and the first and second connectors resist disconnection of the shelf from the support by force applied to the shelf in a direction that is normal to the support.
    Type: Grant
    Filed: March 6, 2019
    Date of Patent: May 31, 2022
    Assignee: CLICKSTAIR PTY LTD
    Inventors: Thomas Fletcher Acquroff, Darren Brink
  • Publication number: 20220076010
    Abstract: A method of generating text features from a document comprises one or more processors grouping text comprised in the document into multiple logical text blocks, wherein each of the logical text blocks comprises one or more tokens. One of the logical text blocks is selected for generating features. Thereafter, logical text blocks neighbouring the selected logical block are identified. Further, the processer qualifies one or more of the neighbouring logical text blocks for generating features. The processor generates features for one or more of the tokens in the selected logical block using the qualified logical text blocks.
    Type: Application
    Filed: September 9, 2020
    Publication date: March 10, 2022
    Inventors: Samuel Peter Thomas FLETCHER, Adam ROEGEIST, Alexander Karl HUDEK
  • Publication number: 20220037574
    Abstract: A thermoelectric device includes each an n-type thermoelectric leg and a p-type thermoelectric leg electrically coupled by an electrical contact. At least one of the n-type and p-type thermoelectric legs contains a particulate semiconductor mixed with hollow microspheres. The hollow microspheres may make up between 40% and 90% by volume of the thermoelectric leg. Adjacent thermoelectric couples may be electrically coupled by a second electrical contact. The thermoelectric legs may be printed by deposition of an ink.
    Type: Application
    Filed: September 17, 2019
    Publication date: February 3, 2022
    Applicant: Sumitomo Chemical Company Limited
    Inventors: Thomas Fletcher, Simon King
  • Publication number: 20210343920
    Abstract: A double layered, flexible thermoelectric generator with direct bonded, double layers of active materials that are directly bonded by heat curing, not soldered nor attached/bonded by an adhesive layer. The thermoelectric device is made from a first substrate and a second substrate, each including an n-type and p-type thermoelectric legs. The first and the second substrate are brought together so that the n-type and p-type thermoelectric legs of the first substrate come into direct contact with, respectively, the n-type and the p-type thermoelectric legs of the second substrate. Each thermoelectric leg may be disposed in a well formed in an insulating layer disposed over contact electrodes supported on the first and second substrate. Each thermoelectric leg may contain a particulate semiconductor and a binder, e.g. a polymer binder. The pairs of legs are bonded together by heat curing.
    Type: Application
    Filed: September 25, 2019
    Publication date: November 4, 2021
    Applicant: Sumitomo Chemical Company Limited
    Inventors: Thomas Fletcher, Simon King, Wichita Koomar-Pokhot
  • Patent number: 11101979
    Abstract: The present invention discloses a method of creating word-level differential privacy with the hashing trick to protect confidentiality of a textual data, the method comprising: receiving a list of a plurality of hashes with a weight (or weights) associated with each of the plurality of hashes; Updating said list with new hashes that are within the range of allowable hash values but not included in said received list of hashes; Updating said list with a new weight to each of said plurality of hashes that are missing said weight; Fitting a probability distribution to said list of said weights of said plurality of hashes; and generating said new weights and said adjusted weights based on sampling of said probability distribution.
    Type: Grant
    Filed: May 30, 2019
    Date of Patent: August 24, 2021
    Assignee: KIRA INC.
    Inventors: Samuel Peter Thomas Fletcher, Alexander Karl Hudek
  • Publication number: 20210143307
    Abstract: Thermoelectric elements and modules for thermoelectric generators with low electrical resistance and/or improved thermovoltage, excellent mechanical stability and flexibility. The thermoelectric elements and modules include stack-type thermoelectric legs formed by lamination of at least two layers comprising semiconductive materials. An adhesive layer may be used to laminate the two layers of semiconductive materials and the stack-type thermoelectric legs may be fabricated by solution deposition methods.
    Type: Application
    Filed: June 14, 2018
    Publication date: May 13, 2021
    Applicant: Sumitomo Chemical Company Limited
    Inventors: Thomas Fletcher, Simon King
  • Publication number: 20210045528
    Abstract: A furniture system is provided having a support to be mounted to an upright structure of a building, and a shelf that is assembled onto the support. The shelf has a load-bearing surface, a front side, and a rear side with a first connector. The support has an outer face that includes at least one second connector. The first and second connectors are configured to interconnect such that, in the assembled the furniture system, the shelf is supported by the support with the load bearing surface projecting horizontally away from the upright structure, the first and second connectors resist rotation of the shelf about the first and second connectors by a force acting downwardly through the load bearing surface, and the first and second connectors resist disconnection of the shelf from the support by force applied to the shelf in a direction that is normal to the support.
    Type: Application
    Filed: March 6, 2019
    Publication date: February 18, 2021
    Inventors: Thomas Fletcher ACQUROFF, Darren BRINK
  • Publication number: 20200382281
    Abstract: The present invention discloses a method of creating word-level differential privacy with the hashing trick to protect confidentiality of a textual data, the method comprising: receiving a list of a plurality of hashes with a weight (or weights) associated with each of the plurality of hashes; Updating said list with new hashes that are within the range of allowable hash values but not included in said received list of hashes; Updating said list with a new weight to each of said plurality of hashes that are missing said weight; Fitting a probability distribution to said list of said weights of said plurality of hashes; and generating said new weights and said adjusted weights based on sampling of said probability distribution.
    Type: Application
    Filed: May 30, 2019
    Publication date: December 3, 2020
    Inventors: Samuel Peter Thomas FLETCHER, Alexander Karl HUDEK
  • Patent number: 10776836
    Abstract: Systems, methods, and computer program products are disclosed for correlating merchant ratings to tipping amounts. In a generalized method, a merchant rating is entered by a user via a user interface. Based upon the merchant rating, the system determines a merchant tip amount, which is then communicated to the user via the interface. Accordingly, merchant ratings and tips are seamlessly integrated with one another.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: September 15, 2020
    Assignee: PAYPAL, INC.
    Inventors: Matthias Patrick Rosch, Thomas Fletcher, Anton Voitovych
  • Patent number: 10740806
    Abstract: Systems, methods, and computer program products are disclosed for correlating tip amounts to merchant ratings. In a generalized method, a merchant tip amount may be entered via a user interface. Based upon the merchant tip amount, the system then determines a corresponding merchant rating. Accordingly, merchant ratings and tips are seamlessly integrated with one another.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: August 11, 2020
    Assignee: PAYPAL, INC.
    Inventors: Matthias Patrick Rosch, Thomas Fletcher, Anton Voitovych
  • Publication number: 20190237647
    Abstract: A method of manufacturing a conductive layer includes the step of dissolving an organic semiconductor polymer in a first solvent, the first solvent being an aromatic or heterocyclic compound comprising one or more electron-rich carbon atom(s) and/or heteroatom(s). The method also includes dissolving a dopant in a second solvent, the second solvent being a polar solvent. The method also includes mixing the solutions of the organic semiconductor polymer and the dopant to form a dispersion comprising doped conductive polymer particles suspended in the solvent blend. The method also includes depositing the dispersion by a solution deposition technique to form a conductive layer. The solution deposition technique is preferably an inkjet printing, dispense printing or drop casting method. The dispersion provides a stable ink composition for the manufacturing of thick and uniform layers with excellent conductivity and thermopower, and allows simple fabrication of thermoelectric legs with enhanced performance.
    Type: Application
    Filed: August 29, 2017
    Publication date: August 1, 2019
    Applicants: Cambridge Display Technology Limited, Sumitomo Chemical Company Limited
    Inventor: Thomas Fletcher
  • Publication number: 20170345068
    Abstract: Systems, methods, and computer program products are disclosed for correlating merchant ratings to tipping amounts. In a generalized method, a merchant rating is entered by a user via a user interface. Based upon the merchant rating, the system determines a merchant tip amount, which is then communicated to the user via the interface. Accordingly, merchant ratings and tips are seamlessly integrated with one another.
    Type: Application
    Filed: May 31, 2016
    Publication date: November 30, 2017
    Inventors: Matthias Patrick Rosch, Thomas Fletcher, Anton Voitovych
  • Publication number: 20170345065
    Abstract: Systems, methods, and computer program products are disclosed for correlating tip amounts to merchant ratings. In a generalized method, a merchant tip amount may be entered via a user interface. Based upon the merchant tip amount, the system then determines a corresponding merchant rating. Accordingly, merchant ratings and tips are seamlessly integrated with one another.
    Type: Application
    Filed: May 31, 2016
    Publication date: November 30, 2017
    Inventors: Matthias Patrick Rosch, Thomas Fletcher, Anton Voitovych
  • Patent number: 9654143
    Abstract: Embodiments of an invention for consecutive bit error detection and correction are disclosed. In one embodiment, an apparatus includes a storage structure, a second storage structure, a parity checker, an error correction code (ECC) checker, and an error corrector. The first storage structure is to store a plurality of data values, a plurality of parity values, and a plurality of ECC values, each parity value corresponding to one of the plurality of data values, a first bit of each parity value corresponding to a first of a plurality of portions of a corresponding data value, wherein the first of the plurality of portions of the corresponding data value is interleaved with a second of the plurality of portions of the corresponding data value, wherein a second bit of each parity value corresponds to a second of the plurality of portions of the corresponding data value, each ECC value corresponding to one of the plurality of data values.
    Type: Grant
    Filed: June 18, 2014
    Date of Patent: May 16, 2017
    Assignee: Intel Corporation
    Inventors: Guillem Sole, Roger Espasa, Sorin Iacobovici, Brian Hickmann, Wei Wu, Thomas Fletcher
  • Patent number: 9424093
    Abstract: A system includes a processor and memory storage units storing software code. The software code comprises code for a scheduling system and for generating a plurality of adaptive partitions that are each associated with one or more process threads and that each have a corresponding processor budget. The code also is executable to, when the system is under a normal load, allocate the processor to one of the threads that is in a ready state and has the highest priority among the process threads that are in a ready state. The code is also executable to, when the system is in overload, allocate the processor to one of the process threads that is in a ready state and has the highest priority among the process threads that are in a ready state and for which the adaptive partition that the process thread is associated with has available guaranteed processor budget.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: August 23, 2016
    Assignee: 2236008 Ontario Inc.
    Inventors: Dan Dodge, Attila Danko, Sebastien Marineau-Mes, Peter van der Veen, Colin Burgess, Thomas Fletcher, Brian Stecher
  • Publication number: 20160179575
    Abstract: An adaptive partition scheduler is a priority-based scheduler that also provides execution time guarantees (fair-share). Execution time guarantees apply to threads or groups of threads when the system is overloaded. When the system is not overloaded, threads are scheduled based strictly on priority, maintaining strict real-time behavior. When the system is overloaded, threads are scheduled based priority of threads that are in a ready state and based on the available guaranteed processor time budget of the adaptive partition associated with each thread.
    Type: Application
    Filed: February 25, 2013
    Publication date: June 23, 2016
    Inventors: Dan Dodge, Attila Danko, Sebastien Marineau-Mes, Peter van der Veen, Colin Burgess, Thomas Fletcher, Brian Stecher