Patents by Inventor Thomas Forsyth

Thomas Forsyth has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Adaptively handling remote atomic execution based upon contention prediction
    Patent number: 8533436
    Abstract: In one embodiment, a method includes receiving an instruction for decoding in a processor core and dynamically handling the instruction with one of multiple behaviors based on whether contention is predicted. If no contention is predicted, the instruction is executed in the core, and if contention is predicted data associated with the instruction is marshaled and sent to a selected remote agent for execution. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: September 10, 2013
    Assignee: Intel Corporation
    Inventors: Joshua B. Fryman, Edward T. Grochowski, Toni Juan, Andrew Thomas Forsyth, John Mejia, Ramacharan Sundararaman, Eric Sprangle, Roger Espasa, Ravi Rajwar
  • SYSTEMS, APPARATUSES, AND METHODS FOR BLENDING TWO SOURCE OPERANDS INTO A SINGLE DESTINATION USING A WRITEMASK
    Publication number: 20120254588
    Abstract: Embodiments of systems, apparatuses, and methods for performing a blend instruction in a computer processor are described. In some embodiments, the execution of a blend instruction causes a data element-by-element selection of data elements of first and second source operands using the corresponding bit positions of a writemask as a selector between the first and second operands and storage of the selected data elements into the destination at the corresponding position in the destination.
    Type: Application
    Filed: April 1, 2011
    Publication date: October 4, 2012
    Inventors: Jesus Corbal San Adrian, Bret L. Toll, Robert C. Valentine, Jeffrey G. Wiedemeier, Sridhar Samudrala, Milind Baburao Girkar, Andrew Thomas Forsyth, Elmoustapha Ould-Ahmed-Vall, Dennis R. Bradford, Lisa K. Wu
  • SYSTEMS, APPARATUSES, AND METHODS FOR EXPANDING A MEMORY SOURCE INTO A DESTINATION REGISTER AND COMPRESSING A SOURCE REGISTER INTO A DESTINATION MEMORY LOCATION
    Publication number: 20120254592
    Abstract: Embodiments of systems, apparatuses, and methods for performing an expand and/or compress instruction in a computer processor are described. In some embodiments, the execution of an expand instruction causes the selection of elements from a source that are to be sparsely stored in a destination based on values of the writemask and store each selected data element of the source as a sparse data element into a destination location, wherein the destination locations correspond to each writemask bit position that indicates that the corresponding data element of the source is to be stored.
    Type: Application
    Filed: April 1, 2011
    Publication date: October 4, 2012
    Inventors: Jesus Corbal San Adrian, Roger Espasa Sans, Robert C. Valentine, Santiago Galan Duran, Jeffrey G. Wiedemeier, Sridhar Samudrala, Milind Baburao Girkar, Andrew Thomas Forsyth, Victor W. Lee
  • Adaptive optimized compare-exchange operation
    Publication number: 20110154000
    Abstract: A technique to perform a fast compare-exchange operation is disclosed. More specifically, a machine-readable medium, processor, and system are described that implement a fast compare-exchange operation as well as a cache line mark operation that enables the fast compare-exchange operation.
    Type: Application
    Filed: December 18, 2009
    Publication date: June 23, 2011
    Inventors: Joshua B. Fryman, Andrew Thomas Forsyth, Edward Grochowski
  • Adaptively Handling Remote Atomic Execution
    Publication number: 20100332801
    Abstract: In one embodiment, a method includes receiving an instruction for decoding in a processor core and dynamically handling the instruction with one of multiple behaviors based on whether contention is predicted. If no contention is predicted, the instruction is executed in the core, and if contention is predicted data associated with the instruction is marshaled and sent to a selected remote agent for execution. Other embodiments are described and claimed.
    Type: Application
    Filed: June 26, 2009
    Publication date: December 30, 2010
    Inventors: Joshua B. Fryman, Edward T. Grochowski, Toni Juan, Andrew Thomas Forsyth, John Mejia, Ramacharan Sundararaman, Eric Sprangle, Roger Espasa, Ravi Rajwar