Abstract: A receiver, for example a receiver of broadcast digital terrestrial television signals modulated using COFDM (Coded Orthogonal Frequency Division Multiplexing), imposes a phase adjustment on a received signal. Phase adjustment may be effected, for example, by sample alignment of the signal, such as for cyclic prefix removal, or by shifting a window setting for a Fast Fourier Transform (FFT) processor. Before channel estimation or decoding is performed on the information stream, the information stream is derotated to compensate for the phase adjustment previously imposed on the received signal.

Abstract: A method and apparatus for a multicarrier receiver circuit with guard interval size detection described. The invention allows the FFT size and guard interval size to be detected quickly even in the presence of relatively noisy input signals. The method is robust in noise environments, and also sufficiently robust to process signals having severe multipath and/or co-channel interference. Moreover, the method is of low complexity, and can be implemented in a VLSI circuit.

Abstract: A method and apparatus for a multicarrier receiver circuit with guard interval size detection described. The invention allows the FFT size and guard interval size to be detected quickly even in the presence of relatively noisy input signals. The method is robust in noise environments, and also sufficiently robust to process signals having severe multipath and/or co-channel interference. Moreover, the method is of low complexity, and can be implemented in a VLSI circuit.

Abstract: A receiver circuit is for processing a received signal which includes at least a first portion and a second portion which repeats the content of the first portion after a repeat interval. For example, the receiver may be for DVB-T signals using COFDM. In order to ensure that the estimated symbol start position is accurate, the receiver calculates two correlation values, namely an early correlation and a late correlation. The early correlation is measured between samples ahead of an assumed first portion start position and ahead of an assumed second portion start position, and the late correlation is measured between samples behind an assumed first portion end position and behind an assumed second portion end position. When the assumed start and end positions are accurate, the early and late correlations are equal, and so the assumed start and end positions are controlled to equalize the early correlation and the late correlation.

Abstract: A method and apparatus for a multicarrier receiver circuit with guard interval size detection is described. The invention allows the FFT size and guard interval size to be detected quickly, even in the presence of relatively noisy input signals. The method is robust in noisy environments, and also sufficiently robust to process signals having severe multipath and/or co-channel interference. Moreover, the method is of low complexity, and can be implemented in a VLSI circuit.

Abstract: A receiver, for example a receiver of broadcast digital terrestrial television signals modulated using COFDM (Coded Orthogonal Frequency Division Multiplexing), imposes a phase adjustment on a received signal. Phase adjustment may be effected, for example, by sample alignment of the signal, such as for cyclic prefix removal, or by shifting a window setting for a Fast Fourier Transform (FFT) processor. Before channel estimation or decoding is performed on the information stream, the information stream is derotated to compensate for the phase adjustment previously imposed on the received signal.

Abstract: The invention provides a single chip implementation of a digital receiver for multicarrier signals that are transmitted by orthogonal frequency division multiplexing. Improved channel estimation and correction circuitry are provided. The receiver has highly accurate sampling rate control and frequency control circuitry. BCH decoding of tps data carriers is achieved with minimal resources with an arrangement that includes a small Galois field multiplier. An improved FFT window synchronization circuit is coupled to the resampling circuit for locating the boundary of the guard interval transmitted with the active frame of the signal. A real-time pipelined FFT processor is operationally associated with the FFT window synchronization circuit and operates with reduced memory requirements.

Abstract: The invention provides a single chip implementation of a digital receiver for multicarrier signals that are transmitted by orthogonal frequency division multiplexing. Improved channel estimation and correction circuitry are provided. The receiver has highly accurate sampling rate control and frequency control circuitry. BCH decoding of tps data carriers is achieved with minimal resources with an arrangement that includes a small Galois field multiplier. An improved FFT window synchronization circuit is coupled to the resampling circuit for locating the boundary of the guard interval transmitted with the active frame of the signal. A real-time pipelined FFT processor is operationally associated with the FFT window synchronization circuit and operates with reduced memory requirements.

Abstract: A method and apparatus for a multicarrier receiver circuit with guard interval size detection is described. The invention allows the FFT size and guard interval size to be detected quickly, even in the presence of relatively noisy input signals. The method is robust in noisy environments, and also sufficiently robust to process signals having severe multipath and/or co-channel interference. Moreover, the method is of low complexity, and can be implemented in a VLSI circuit.

Abstract: The invention provides a single chip implementation of a digital receiver for multicarrier signals that are transmitted by orthogonal frequency division multiplexing. Improved channel estimation and correction circuitry are provided. The receiver has highly accurate sampling rate control and frequency control circuitry. BCH decoding of tps data carriers is achieved with minimal resources with an arrangement that includes a small Galois field multiplier. An improved FFT window synchronization circuit is coupled to the resampling circuit for locating the boundary of the guard interval transmitted with the active frame of the signal. A real-time pipelined FFT processor is operationally associated with the FFT window synchronization circuit and operates with reduced memory requirements.

Abstract: The invention provides a decoder of symbols of received data, the data being encoded according to a convolutional encoding scheme and transmitted through a communications channel. The data is punctuated according to a puncturing matrix, and has a plurality of state values which describe a sequence of state transitions. The decoder has a generation unit that accepts the received data for calculating metrics of the transitions thereof. A selector responsive to the generation unit selects a path of transitions corresponding to the path produced by a transmitter of the data stream. A traceback unit maintains historical information representative of sequential decision operations of the selector. A counter is provided for counting illegal state transitions of the path selected by the selector, and a control unit, responsive to the counter, determines a puncture rate and adjusts a puncture phase of the received data.

Abstract: A Reed-Solomon decoder includes an optimized Galois Field multiplication circuit. The circuit has a plurality of multipliers, connected in a linear chain, wherein a first multiplicand of the first multiplier is the magnitude A, and the second multiplicand is a constant. The circuit operates on a linear combination of alpha values that sum to .alpha..sup.j, each multiplier in the chain generating a succeeding alpha value. A plurality of selectors enable the outputs of the multipliers according to the magnitude .alpha..sup.j. An addition circuit, preferably realized as a logical network of XOR gates, is connected to the selectors for adding the enabled outputs of the multipliers to form the final product.

Abstract: The invention provides a decoder of symbols of received data, the data being encoded according to a convolutional encoding scheme and transmitted through a communications channel. The data is punctuated according to a puncturing matrix, and has a plurality of state values which describe a sequence of state transitions. The decoder has a generation unit that accepts the received data for calculating metrics of the transitions thereof. A selector responsive to the generation unit selects a path of transitions corresponding to the path produced by a transmitter of the data stream. A traceback unit maintains historical information representative of sequential decision operations of the selector. A counter is provided for counting illegal state transitions of the path selected by the selector, and a control unit, responsive to the counter, determines a puncture rate and adjusts a puncture phase of the received data.