Patents by Inventor Thomas Francis Lum

Thomas Francis Lum has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Test structure for enabling burn-in testing on an entire semiconductor wafer
    Patent number: 5959462
    Abstract: A test structure and test methodology are taught herein wherein a test structure (10) is used to test an entire integrated circuit product wafer (44). The test structure (10) has a backing support wafer (39). A die attach compound (38) is used to attach a plurality of segmented individual test integrated circuits 28-34 to the backing support wafer (39). The plurality of test integrated circuits 28-34 have a top conductive bump layer (26). This conductive bump layer (26) is contacted to a thin film signal distribution layer (14) which contains conductive interconnects, conductive layers, and dielectric layers which route electrical signals as illustrated in FIG. 2. The layer 14 also conductively connects to bumps (46) on a product wafer (44). In addition, leads (40) are coupled to conductive elements of the layer (14).
    Type: Grant
    Filed: September 8, 1997
    Date of Patent: September 28, 1999
    Assignee: Motorola, Inc.
    Inventor: Thomas Francis Lum
  • Test structure and method for performing burn-in testing of a semiconductor product wafer
    Patent number: 5707881
    Abstract: A test structure and test methodology are taught herein wherein a test structure (10) is used to test an entire integrated circuit product wafer (44). The test structure (10) has a backing support wafer (39). A die attach compound (38) is used to attach a plurality of segmented individual test integrated circuits 28-34 to the backing support wafer (39). The plurality of test integrated circuits 28-34 have a top conductive bump layer (26). This conductive bump layer (26) is contacted to a thin film signal distribution layer (14) which contains conductive interconnects, conductive layers, and dielectric layers which route electrical signals as illustrated in FIG. 2 . The layer 14 also conductively connects to bumps (46) on a product wafer (44). In addition, leads (40) are coupled to conductive elements of the layer (14).
    Type: Grant
    Filed: September 3, 1996
    Date of Patent: January 13, 1998
    Assignee: Motorola, Inc.
    Inventor: Thomas Francis Lum