Abstract: A traffic shaping circuit regulates packets transferred by a transmission resource into a network (e.g., a network on a chip) on behalf of a client. The packet transfers are selectively enabled or disabled based on a current budget value. The budget value is modified based on a packet-transfer cost in response to transferring a packet into the network. The rate of packet transfers into the network is monitored. A cost-adjustment signal is generated based on the rate of packet transfers. The packet-transfer cost is modified in response to the cost-adjustment signal for accounting for a subsequent-packet transfer into the network. The cost-adjustment signal may indicate an increase or decrease of the packet-transfer cost and/or a budget limit, both of which are read from a cost table comprising records ordered based on respective packet-transfer cost values. The packet-transfer cost and/or a budget limit are configurable.

Abstract: A filter for performing access control list (ACL) filtering may be used in place of highly-complex and resource-intensive TCAMs for access control. In this regard, the filter may be configured to compare packet header information to action-priority pairs stored in ACL tables. Each action-priority pair indicates at least one action to be performed for implementing a desired rule and a priority for that action. An access control action from an action-priority pair matching the header information may be performed in order to implement a desired access control rule for the received packet. If multiple action-priority pairs from the same table match the header information, then the priorities of the matching action-priority pairs may be compared to resolve the conflict. The circuitry of the filter is arranged such that exact-match searching can be performed on the ACL tables to reduce the complexity and cost of the filter.

Abstract: A traffic shaping circuit regulates packets transferred by a transmission resource into a network (e.g., a network on a chip) on behalf of a client. The packet transfers are selectively enabled or disabled based on a current budget value. The budget value is modified based on a packet-transfer cost in response to transferring a packet into the network. The rate of packet transfers into the network is monitored. A cost-adjustment signal is generated based on the rate of packet transfers. The packet-transfer cost is modified in response to the cost-adjustment signal for accounting for a subsequent-packet transfer into the network. The cost-adjustment signal may indicate an increase or decrease of the packet-transfer cost and/or a budget limit, both of which are read from a cost table comprising records ordered based on respective packet-transfer cost values. The packet-transfer cost and/or a budget limit are configurable.

Abstract: A network switch allocates large-scale memory units as data packets are received in order to implement per-queue, circular egress buffers. Each large-scale memory unit is larger than the maximum packet length of the received packets and is capable of storing a plurality of data packets, thereby reducing the number of memory allocation events that are required to process a given number of data packets. Efficient techniques for writing to and reading from the large-scale egress memory units have been developed and may be used to reduce processing delays. Such techniques are compatible with relatively inexpensive memory devices, such as dynamic random access memory (DRAM), that may be separate from the circuitry used to process the data packets. The described architectures are easily scalable so that that a large number of ports (e.g., thousands) may be implemented at a relatively low cost and complexity without introducing significant processing delays.

Abstract: A memory system has a plurality of memory stages in which each stage stores a respective portion of a data table. A request for reading an entry of the table is processed serially by the memory stages, and each stage narrows the range of table entries possibly storing the requested data. Based on the results of the previous stages, the final stage is able to quickly determine whether the requested data is stored in the data table and, if so, to retrieve the requested data from such table.

Abstract: The physical layer of an optical line terminal (OLT) of an optical network is split across multiple fibers so that the OLT has a plurality of optical transceivers for respectively communicating across a plurality of optical fibers. Thus, each optical transceiver is in communication with a smaller number of optical network units (ONUs) relative to an embodiment for which a single optical transceiver is employed, thereby reducing the transmit power requirements of the optical network. Accordingly, less expensive optical components, such as lasers, can be used at the OLT and the ONUs. In addition, the split at the OLT is implemented digitally, and the digital components of the OLT are arranged such that various performance benefits are realized. As an example, the OLT may be configured such that data and/or overhead may be simultaneously transmitted in the upstream direction thereby increasing the upstream throughput and capacity of the optical network.

Abstract: Egress of data packets from a packet switch is controlled in a manner that involves adjusting the shaper accumulators only when a packet egress event or accumulator credit threshold event occurs. A timeline having a number of timeslots is maintained in a memory to mark the times at which events are predicted to occur. If an egress event occurs, in which one or more data packets have been sent from a queue, or if the current timeslot contains a marker, then a count stored in an accumulator is adjusted. If an egress event has occurred or a threshold event in which a count stored in an accumulator has crossed a threshold has occurred, then a marker is stored in a future timeslot.

Abstract: Egress of data packets from a packet switch is controlled in a manner that involves adjusting the shaper accumulators only when a packet egress event or accumulator credit threshold event occurs. A timeline having a number of timeslots is maintained in a memory to mark the times at which events are predicted to occur. If an egress event occurs, in which one or more data packets have been sent from a queue, or if the current timeslot contains a marker, then a count stored in an accumulator is adjusted. If an egress event has occurred or a threshold event in which a count stored in an accumulator has crossed a threshold has occurred, then a marker is stored in a future timeslot.