Abstract: An integrated circuit data processor receives interrupt level signals from external circuitry which represent a priority level associated with the external circuitry. These signals are compared with signals representing the current operating level of the processor, and an interrupt pending output is generated if (1) the priority level is higher than the operating level; or (2) a maximum priority level is received. Upon the occurrence of the interrupt pending output, the current instruction program is interrupted, and an instruction program associated with the external circuitry is executed. The processor transmits a signal back to the external circuitry indicating that the interrupt request has been granted and receives a vector number from the external circuitry. A first acknowledgment signal from the external circuitry causes the vector number to be latched in the processor. A second acknowledgment signal from the external circuitry causes a vector to be internally generated.

Abstract: An integrated circuit microprocessor includes storage means coupled to a control unit for receiving from the control unit information regarding how the next bus cycle is to be run. Upon receipt of a bus error signal from a peripheral device, the storage means is reset. If, however, a halt signal accompanies the bus error signal, the storage means is not reset and the bus cycle is rerun when the halt signal terminates.

Abstract: Each channel of a priority encoder register is equipped with a latch for storing one bit of a binary data word. The channel of highest priority generates an output which is applied to encoding means which in turn generates a unique code. The channel output is also fed back to reset its associated latch to permit the channel of next highest priority to generate an output.

Abstract: A data processor which includes an instruction register for storing a macroinstruction to be executed, a decoder responsive to the stored macroinstruction for generating two or more starting addresses, and a selector which receives the starting addresses generated by the decoder and which selects one of the starting addresses as a next address in response to one or more selection signals. The data processor also includes a control structure which receives the next address chosen by the selector and which selects one of the starting addresses as a next address in response to one or more selection signals. The data processor also icludes a control structure which receives the next address chosen by the selector and which, in response to the next address, derives the selection signals to which the selector will respond in order to select a subsequent next address.

Abstract: A data processor having a microprogrammed control store and including a conditional branch control unit for receiving selection bits output by the control store, selection bits from an instruction register, and conditional signals for generating a two-bit result which, when added to a base address, can specify one of two, three, or four branch destinations in the control store. The selection bits output by the control store determine whether the combination of conditional signals upon which the branch is dependent is selected by the control store or is selected directly by a bit field in the macroinstruction. Also, one of the selection bits output by the control store is used to select one of two possible output codes for the two-bit result associated with a particular branch destination.

Abstract: A data processor having an execution unit and which includes a control means having a first and a second control store. The control means has an input for receiving a control store address. In response to the received control store address, the first control store provides sequencing information at a first output for selecting the next control store address. Also, in response to the received control store address, the second control store supplies control information at a second output for controlling the execution unit. The data processor also includes means for receiving a macroinstruction and selection means responsive to the macroinstruction and to the sequencing information for generating the control store address. In a preferred embodiment, the control store address is received by both the input of the first control store and the input of the second control store. Each control word in the first control store has a unique control store address.

Abstract: A microprocessor interconnected to a RAM on the same integrated circuit chip. Interconnect circuitry connects the RAM to the microprocessor data bus to allow RAM data to be transferred to an instruction register of the microprocessor which permits the RAM to contain instructions and operation codes. A sense amplifier is used to provide an output from the RAM. At least one buffer is coupled to the output of the sense amplifier. A bilateral switch is coupled to the at least one buffer and controllably switches the output of the at least one buffer to the microprocessor internal data bus and to an external data bus.

Abstract: A data processor which is adapted for microprogrammed operation has a control store includes an ALU and condition code control unit for controlling operations performed by an arithmetic-logic unit within the execution unit of the data processor and for controlling the setting of the condition code bits in a status register. The ALU and condition code control unit is arranged in a row and column format. A decoder coupled to a macroinstruction register selects a row which is selected over an entire period that is required to execute macroinstruction. The row corresponds to a set of operations and condition code settings associated with a particular macroinstruction. The control store output provides information for selecting the proper column during each microcycle used to execute the macroinstruction. ALU function control signals and the condition code control signals are selected simultaneously according to the selected row and column.

Abstract: A microprogrammed control structure for an integrated circuit data processor which employs a two-level control store designated as a micro control store and nano control store. An instruction decoder decodes each macro instruction to be executed by the data processor and causes a series of micro word addresses to be input to the micro control store. In response to such input, the micro control store outputs a corresponding number of nano address words for addressing the nano control store. The nano control store when addressed by the nano address words, outputs a control word to an execution unit for executing the macro instruction.

Abstract: A data processor having an execution unit employs a segmented bus structure and a dual port register cell in order to increase circuit density and in order to allow address and data computations to occur simultaneously. The circuit is designed to interface with an external 16-bit bidirectional data bus and an external address bus having as many as 32 address bits. Serial bus switches on each of two parallel buses allow concatenation with a second pair of buses. Each bus, while 16 bits wide, actually utilizes two conductors per bit to carry data and the complement thereof.