Abstract: Driving address translations in a microprocessor system by sending a rejected Lx+1 cache request from a first set of caches of a first level Lx to a central request unit, transferring an Lx+1 cache request having a translation of a virtual address into a physical address stored in a first buffer, from the central request unit to the at least one Lx+1 cache, and keeping an Lx+1 cache request lacking a translation of a virtual address into a physical address stored in the first buffer, pending in the central request unit.

Abstract: Driving address translations in a microprocessor system by sending a rejected Lx+1 cache request from a first set of caches of a first level Lx to a central request unit, transferring an Lx+1 cache request having a translation of a virtual address into a physical address stored in a first buffer, from the central request unit to the at least one Lx+1 cache, and keeping an Lx+1 cache request lacking a translation of a virtual address into a physical address stored in the first buffer, pending in the central request unit.

Abstract: The present disclosure relates to a method of operating a hierarchical translation lookaside buffer (TLB). The TLB comprises at least two TLB levels, wherein a given entry of the upper level TLB comprises a portion of bits for indicating related entries in the lower level TLB. The method comprises the following when a TLB miss is encountered for a requested first virtual address. A first table walk is performed to obtain the absolute memory address for the first virtual address. A logical tag is stored. The logical tag comprises the portion of bits that has been identified in association with the first table walk. In response to determining that a concurrent second table walk, of the ongoing first table walk, that has a second virtual address that addresses the same entry in the upper level TLB as the first virtual address is writing in the TLB, the stored logical tag may be incremented. And, the incremented logical tag and the obtained absolute memory address may be stored in the TLB.

Abstract: The present disclosure relates to a method of operating a hierarchical translation lookaside buffer (TLB). The TLB comprises at least two TLB levels, wherein a given entry of the upper level TLB comprises a portion of bits for indicating related entries in the lower level TLB. The method comprises the following when a TLB miss is encountered for a requested first virtual address. A first table walk is performed to obtain the absolute memory address for the first virtual address. A logical tag is stored. The logical tag comprises the portion of bits that has been identified in association with the first table walk. In response to determining that a concurrent second table walk, of the ongoing first table walk, that has a second virtual address that addresses the same entry in the upper level TLB as the first virtual address is writing in the TLB, the stored logical tag may be incremented. And, the incremented logical tag and the obtained absolute memory address may be stored in the TLB.