Abstract: An amplifier includes an input transistor pair connected to amplifier input nodes, a complementary transistor pair connected to a common bias, amplifier output nodes connected to the input transistor pair and the complementary transistor pair, and variable capacitors connected between the complementary transistor pair and the amplifier output nodes.

Abstract: An amplifier includes an input transistor pair connected to amplifier input nodes, a complementary transistor pair connected to a common bias, amplifier output nodes connected to the input transistor pair and the complementary transistor pair, and variable capacitors connected between the complementary transistor pair and the amplifier output nodes.

Abstract: Embodiments of the present disclosure provide a circuit structure. An error amplifier of the structure includes an input terminal coupled to a voltage source, a reference terminal, and an output terminal coupled to a back-gate terminal of a power amplifier. A voltage at the output terminal of the error amplifier indicates a voltage difference between the input terminal and the reference terminal. A logarithmic current source may be coupled to the reference terminal of the error amplifier, the logarithmic current being configured to generate a reference current logarithmically proportionate to a voltage level of the voltage source. A plurality of serially coupled transistor cells, having a shared substrate and coupled between the reference terminal of the error amplifier and ground, each may include a back-gate terminal coupled to the output terminal of the error amplifier.

Abstract: Embodiments of the present disclosure provide a circuit structure including: a first transistor having a gate terminal, a source terminal, a drain terminal, and a back-gate terminal electrically coupled to an adjustable voltage source. The gate terminal of the first transistor is electrically coupled to a first node having a first bias voltage. A second transistor has a gate terminal, a source terminal electrically coupled to the drain terminal of the first transistor, a drain terminal, and a back-gate terminal electrically connected to the adjustable voltage source. The gate terminal of the second transistor is electrically coupled to a second node having a second bias voltage. The adjustable voltage source is selectable between a first voltage and a second voltage to control a threshold voltage of the first transistor and a threshold voltage of the second transistor.

Abstract: Embodiments of the present disclosure provide a circuit structure. An error amplifier of the structure includes an input terminal coupled to a voltage source, a reference terminal, and an output terminal coupled to a back-gate terminal of a power amplifier. A voltage at the output terminal of the error amplifier indicates a voltage difference between the input terminal and the reference terminal. A logarithmic current source may be coupled to the reference terminal of the error amplifier, the logarithmic current being configured to generate a reference current logarithmically proportionate to a voltage level of the voltage source. A plurality of serially coupled transistor cells, having a shared substrate and coupled between the reference terminal of the error amplifier and ground, each may include a back-gate terminal coupled to the output terminal of the error amplifier.

Abstract: Methods form amplifier device structures that include first-third amplifier devices. The first amplifier device produces an intermediate signal. The second amplifier device is connected to an input of the first amplifier device and produces an amplified inverted output signal. The third amplifier device inverts the intermediate signal to produce an amplified non-inverted output signal that is complementary to the amplified inverted output signal. A resistor feedback loop is connected to the input and output of the first amplifier device. A gain ratio of the gain of the third amplifier device to the gain of the second amplifier device matches a resistance ratio of the source resistance of the input signal to the resistance of the resistor added to the source resistance. Also, DC loop circuits are connected to the first-third amplifier devices, and each of the DC loop circuits connects an amplifier device output to an amplifier device input.

Abstract: Disclosed are integrated circuit (IC) structure embodiments with a three-dimensional (3D) metal-insulator-metal capacitor (MIMCAP) in back-end-of-the-line (BEOL) metal levels. The MIMCAP includes a plurality of high aspect ratio trenches that extend through at least one relatively thick dielectric layer within the metal levels. Conformal layers of a metal, an insulator and another metal line the trenches and cover the top of the dielectric layer in the area of the MIMCAP. Different configurations for the bottom and top electrode contacts can be used including, for example, one configuration where the top electrode contact is a dual-damascene structure within an ultra-thick metal (UTM) level above the MIMCAP and another configuration where both the top and bottom electrode contacts are such dual-damascene structures.

Abstract: Disclosed are integrated circuit (IC) structure embodiments with a three-dimensional (3D) metal-insulator-metal capacitor (MIMCAP) in back-end-of-the-line (BEOL) metal levels. The MIMCAP includes a plurality of high aspect ratio trenches that extend through at least one relatively thick dielectric layer within the metal levels. Conformal layers of a metal, an insulator and another metal line the trenches and cover the top of the dielectric layer in the area of the MIMCAP. Different configurations for the bottom and top electrode contacts can be used including, for example, one configuration where the top electrode contact is a dual-damascene structure within an ultra-thick metal (UTM) level above the MIMCAP and another configuration where both the top and bottom electrode contacts are such dual-damascene structures.

Abstract: Methods form amplifier device structures that include first-third amplifier devices. The first amplifier device produces an intermediate signal. The second amplifier device is connected to an input of the first amplifier device and produces an amplified inverted output signal. The third amplifier device inverts the intermediate signal to produce an amplified non-inverted output signal that is complementary to the amplified inverted output signal. A resistor feedback loop is connected to the input and output of the first amplifier device. A gain ratio of the gain of the third amplifier device to the gain of the second amplifier device matches a resistance ratio of the source resistance of the input signal to the resistance of the resistor added to the source resistance. Also, DC loop circuits are connected to the first-third amplifier devices, and each of the DC loop circuits connects an amplifier device output to an amplifier device input.

Abstract: Embodiments of the present disclosure provide a circuit structure including: a first transistor having a gate terminal, a source terminal, a drain terminal, and a back-gate terminal electrically coupled to an adjustable voltage source. The gate terminal of the first transistor is electrically coupled to a first node having a first bias voltage. A second transistor has a gate terminal, a source terminal electrically coupled to the drain terminal of the first transistor, a drain terminal, and a back-gate terminal electrically connected to the adjustable voltage source. The gate terminal of the second transistor is electrically coupled to a second node having a second bias voltage. The adjustable voltage source is selectable between a first voltage and a second voltage to control a threshold voltage of the first transistor and a threshold voltage of the second transistor.

Abstract: Comparators include (among other components) two inputs, an output, and two pairs of transistors (each connected to a different one of the inputs). Both pairs of transistors are connected to the output. Additionally, a first signal generator is connected to the first transistor in each of the pairs of transistors, and a second signal generator is connected to the second transistor in each of the pairs of transistors. The first signal generator and the second signal generator output on/off control signals that have timing patterns that are inverted relative to one another, and this causes only the first transistor or the second transistor in each of the pairs of transistors to be active at any given time. Thus, the single active transistor in the first pair of transistors and the single active transistor in the second pair of transistors amplify the difference between the two inputs, through the output.

Abstract: At least one method, apparatus and system disclosed involves providing semiconductor device having transistors comprising back gates and front gates. The semiconductor device comprises a signal processing unit for processing an input signal to provide an output signal. The signal processing unit includes a first transistor and a second transistor. The first transistor includes a first back gate electrically coupled to a first front gate. The signal processing unit also includes a second transistor operatively coupled to the first transistor. The second transistor includes a second back gate electrically coupled to a second front gate. The semiconductor device also includes a gain circuit for providing a gain upon the output signal. The semiconductor device also includes a bias circuit to provide a first bias signal to the first back gate and a second bias signal to the second back gate.

Abstract: At least one method, apparatus and system disclosed involves providing semiconductor device having transistors comprising back gates and front gates. The semiconductor device comprises a signal processing unit for processing an input signal to provide an output signal. The signal processing unit includes a first transistor and a second transistor. The first transistor includes a first back gate electrically coupled to a first front gate. The signal processing unit also includes a second transistor operatively coupled to the first transistor. The second transistor includes a second back gate electrically coupled to a second front gate. The semiconductor device also includes a gain circuit for providing a gain upon the output signal. The semiconductor device also includes a bias circuit to provide a first bias signal to the first back gate and a second bias signal to the second back gate.

Abstract: An RF MOS transistor having improved AC output conductance and AC output capacitance includes parallel interdigitated source and drain regions separated by channel regions and overlying gates. Grounded tap regions contacting an underlying well are placed contiguous to source regions and reduce distributed backgate resistance, lower backgate channel modulation, and lower output conductance.

Abstract: An RF MOS transistor having improved AC output conductance and AC output capacitance includes parallel interdigitated source and drain regions separated by channel regions and overlying gates. Grounded tap regions contacting an underlying well are placed contiguous to source regions and reduce distributed backgate resistance, lower backgate channel modulation, and lower output conductance.

Abstract: Disclosed is a frequency conversion circuit with sideband suppression in which a first mixer receives an in-phase signal (IFi) and is driven by a local oscillator having an in-phase (0°) oscillator signal (LOi), and produces two sideband signals (LO+IF, LO−IF). A second mixer receives a quadrature phase frequency signal (IFq+) and is driven by a local oscillator having a quadrature (180°) oscillator signal (LOq), and produces two sideband signals (LO+IFq, LO−IFq). One of the sidebands from the second mixer is 180° out of phase with respect to the same sideband from the first mixer. A signal combiner then receives and combines the two sidebands from the first mixer and the two sidebands from the second mixer, the signal combiner suppressing one sideband and enhancing the other sideband. In preferred embodiments, the mixers comprise MOSFET transistors and the signal combiner comprises capacitive elements.

Abstract: An RF MOS transistor having improved AC output conductance and AC output capacitance includes parallel interdigitated source and drain regions separated by channel regions and overlying gates. Grounded tap regions contacting an underlying well are placed contiguous to source regions and reduce distributed backgate resistance, lower backgate channel modulation, and lower output conductance.

Abstract: Disclosed is a CMOS transistor amplifier for small RF signals which operates in a Class AB mode. The serially connected P channel and N channel transistors of the CMOS transistor pair have DC bias voltages applied to the control gates, and the small input signal is capacitively coupled to the gates of the CMOS transistor pair. In a preferred embodiment, the DC voltage bias for the P channel transistor is derived from a second P channel transistor which is approximately identical to the first P channel transistor in structure with the second P channel transistor serially connected with the current source and the voltage at the gate/drain of the transistor resistively coupled to the gate of the first P channel transistor.

Abstract: Embodiments of the present invention provide a seal ring which includes a plurality of cuts separating the seal ring into seal ring portions which are disposed adjacent to different circuits in the integrated circuit die. The cuts reduce the noise coupling among the different circuits through the seal ring. To further isolate the sensitive RF/analog circuits from the noise generated by the digital circuit, the seal ring may be electrically (for dc noise) isolated from the substrate. This is accomplished, for instance, by inserting a polysilicon layer and gate oxide between the seal ring and the substrate. In addition, an n-well/p-well capacitor may be formed in series with the gate oxide, for instance, by implanting an n-well below the polysilicon layer in a p-type substrate.

Abstract: Disclosed is a frequency conversion circuit with sideband suppression in which a first mixer receives an in-phase signal (IFi) and is driven by a local oscillator having an in-phase (0°) oscillator signal (LOi), and produces two sideband signals (LO+IF, LO−IF). A second mixer receives a quadrature phase frequency signal (IFq+) and is driven by a local oscillator having a quadrature (180°) oscillator signal (LOq), and produces two sideband signals (LO+IFq, LO−IFq). One of the sidebands from the second mixer is 180° out of phase with respect to the same sideband from the first mixer. A signal combiner then receives and combines the two sidebands from the first mixer and the two sidebands from the second mixer, the signal combiner suppressing one sideband and enhancing the other sideband. In preferred embodiments, the mixers comprise MOSFET transistors and the signal combiner comprises capacitive elements.